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ORCIDAndreas Gerstlauer
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- affiliation: University of Texas at Austin, USA
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2020 – today
- 2024
[j41]Erika S. Alcorta
, Mahesh Madhav, Richard Afoakwa, Scott Tetrick, Neeraja J. Yadwadkar, Andreas Gerstlauer:
Characterizing Machine Learning-Based Runtime Prefetcher Selection. IEEE Comput. Archit. Lett. 23(2): 146-149 (2024)- [j40]Vishnuvardhan V. Iyer, Aditya Thimmaiah, Michael Orshansky, Andreas Gerstlauer, Ali E. Yilmaz:
A Hierarchical Classification Method for High-accuracy Instruction Disassembly with Near-field EM Measurements. ACM Trans. Embed. Comput. Syst. 23(1): 10:1-10:21 (2024) - [c114]James A. Boyle, Mark Plagge, Suma George Cardwell, Frances S. Chance, Andreas Gerstlauer:
Tutorial: Large-Scale Spiking Neuromorphic Architecture Exploration using SANA-FE. CODES+ISSS 2024: 1-2 - [c113]Endri Taka, Dimitrios Gourounas, Andreas Gerstlauer, Diana Marculescu, Aman Arora:
Efficient Approaches for GEMM Acceleration on Leading AI-Optimized FPGAs. FCCM 2024: 54-65 - [c112]Alexander Cathis, Ge Li, Shijia Wei, Michael Orshansky, Mohit Tiwari, Andreas Gerstlauer:
SoK Paper: Power Side-Channel Malware Detection. HASP@MICRO 2024: 1-9 - [i10]Endri Taka, Dimitrios Gourounas, Andreas Gerstlauer, Diana Marculescu, Aman Arora:
Efficient Approaches for GEMM Acceleration on Leading AI-Optimized FPGAs. CoRR abs/2404.11066 (2024) - [i9]Madison Threadgill, Andreas Gerstlauer:
A Survey of Distributed Learning in Cloud, Mobile, and Edge Settings. CoRR abs/2405.15079 (2024) - [i8]Pranav Rama, Madison Threadgill, Andreas Gerstlauer:
Distributed Convolutional Neural Network Training on Mobile and Edge Clusters. CoRR abs/2409.09083 (2024) - 2023
- [j39]Ajay Krishna Ananda Kumar, Sami Alsalamin, Hussam Amrouch, Andreas Gerstlauer:
Machine Learning-Based Microarchitecture- Level Power Modeling of CPUs. IEEE Trans. Computers 72(4): 941-956 (2023) - [j38]Erika Susana Alcorta Lozano, Andreas Gerstlauer:
Learning-based Phase-aware Multi-core CPU Workload Forecasting. ACM Trans. Design Autom. Electr. Syst. 28(2): 23:1-23:27 (2023) - [c111]Dimitrios Gourounas, Bagus Hanindhito, Arash Fathi, Dimitar Trenev, Lizy K. John, Andreas Gerstlauer:
FAWS: FPGA Acceleration of Large-Scale Wave Simulations. ASAP 2023: 76-84 - [c110]Erika S. Alcorta, Andreas Gerstlauer, Chenhui Deng, Qi Sun, Zhiru Zhang, Ceyu Xu, Lisa Wu Wills, Daniela Sanchez Lopera, Wolfgang Ecker, Siddharth Garg, Jiang Hu:
Special Session: Machine Learning for Embedded System Design. CODES+ISSS 2023: 28-37 - [c109]Ahsan Saeed, Denis Hoornaert, Dakshina Dasari, Dirk Ziegenbein, Daniel Mueller-Gritschneder, Ulf Schlichtmann, Andreas Gerstlauer, Renato Mancuso:
Memory Latency Distribution-Driven Regulation for Temporal Isolation in MPSoCs. ECRTS 2023: 4:1-4:23 - [c108]Dimitrios Gourounas, Bagus Hanindhito, Arash Fathi, Dimitar Trenev, Lizy Kurian John, Andreas Gerstlauer:
LAWS: Large-Scale Accelerated Wave Simulations on FPGAs. FPGA 2023: 230 - [c107]James A. Boyle, Mark Plagge, Suma George Cardwell, Frances S. Chance, Andreas Gerstlauer:
Performance and Energy Simulation of Spiking Neuromorphic Architectures for Fast Exploration. ICONS 2023: 19:1-19:4 - [i7]Erika S. Alcorta, Mahesh Madhav, Scott Tetrick, Neeraja J. Yadwadkar, Andreas Gerstlauer:
Lightweight ML-based Runtime Prefetcher Selection on Many-core Platforms. CoRR abs/2307.08635 (2023) - 2022
- [j37]Andreas Gerstlauer, Aviral Shrivastava:
Report on the 2021 Embedded Systems Week (ESWEEK). IEEE Des. Test 39(1): 94-96 (2022) - [j36]Mochamad Asri, Andreas Gerstlauer:
CASPHAr: Cache-Managed Accelerator Staging and Pipelining in Heterogeneous System Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4325-4336 (2022) - [j35]Francisco Javier Hernandez Santiago, Honglan Jiang, Hussam Amrouch, Andreas Gerstlauer, Leibo Liu, Jie Han:
Characterizing Approximate Adders and Multipliers for Mitigating Aging and Temperature Degradations. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4558-4571 (2022) - [j34]Armin Alaghi, Eva Darulova, Andreas Gerstlauer, Phillip Stanley-Marbell:
Introduction to the Special Issue on Approximate Systems. ACM Trans. Design Autom. Electr. Syst. 27(2): 10:1-10:2 (2022) - [c106]Bagus Hanindhito, Dimitrios Gourounas, Arash Fathi, Dimitar Trenev, Andreas Gerstlauer, Lizy K. John:
GAPS: GPU-acceleration of PDE solvers for wave simulation. ICS 2022: 30:1-30:13 - [c105]Jackson Farley, Andreas Gerstlauer:
MAFAT: Memory-Aware Fusing and Tiling of Neural Networks for Accelerated Edge Inference. IESS 2022: 78-88 - [c104]Ahsan Saeed, Dakshina Dasari, Dirk Ziegenbein, Varun Rajasekaran, Falk Rehm, Michael Pressler, Arne Hamann, Daniel Mueller-Gritschneder, Andreas Gerstlauer, Ulf Schlichtmann:
Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal Isolation in Multi-Cores. RTAS 2022: 133-145 - [c103]Aditya Thimmaiah, Vishnuvardhan V. Iyer, Andreas Gerstlauer, Michael Orshansky:
High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel Attacks. SAMOS 2022: 155-170 - 2021
- [j33]Phillip Stanley-Marbell, Armin Alaghi, Michael Carbin, Eva Darulova, Lara Dolecek, Andreas Gerstlauer, Ghayoor Gillani, Djordje Jevdjic, Thierry Moreau, Mattia Cacciotti, Alexandros Daglis, Natalie D. Enright Jerger, Babak Falsafi, Sasa Misailovic, Adrian Sampson, Damien Zufferey:
Exploiting Errors for Efficiency: A Survey from Circuits to Applications. ACM Comput. Surv. 53(3): 51:1-51:39 (2021) - [j32]Tulika Mitra, Andreas Gerstlauer:
Report on the 2020 Embedded Systems Week (ESWEEK): A Virtual Event during a Pandemic, September 20-25. IEEE Des. Test 38(1): 79-80 (2021) - [j31]Rafael Stahl, Alexander Hoffman, Daniel Mueller-Gritschneder, Andreas Gerstlauer, Ulf Schlichtmann:
DeeperThings: Fully Distributed CNN Inference on Resource-Constrained Edge Devices. Int. J. Parallel Program. 49(4): 600-624 (2021) - [j30]Furkan Aydin, Aydin Aysu, Mohit Tiwari, Andreas Gerstlauer, Michael Orshansky:
Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols. ACM Trans. Embed. Comput. Syst. 20(6): 110:1-110:22 (2021) - [j29]Mochamad Asri, Dhairya Malhotra, Jiajun Wang, George Biros, Lizy K. John, Andreas Gerstlauer:
Hardware Accelerator Integration Tradeoffs for High-Performance Computing: A Case Study of GEMM Acceleration in N-Body Methods. IEEE Trans. Parallel Distributed Syst. 32(8): 2035-2048 (2021) - [j28]Tanfer Alan, Andreas Gerstlauer, Jörg Henkel:
Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1231-1243 (2021) - [c102]Georgios Zervakis, Hassaan Saadat, Hussam Amrouch, Andreas Gerstlauer, Sri Parameswaran, Jörg Henkel:
Approximate Computing for ML: State-of-the-art, Challenges and Visions. ASP-DAC 2021: 189-196 - [c101]Bagus Hanindhito, Ruihao Li, Dimitrios Gourounas, Arash Fathi, Karan Govil, Dimitar Trenev, Andreas Gerstlauer, Lizy Kurian John:
Wave-PIM: Accelerating Wave Simulation Using Processing-in-Memory. ICPP 2021: 8:1-8:11 - [c100]Qinzhe Wu, Jonathan Beard, Ashen Ekanayake, Andreas Gerstlauer, Lizy K. John:
Virtual-Link: A Scalable Multi-Producer Multi-Consumer Message Queue Architecture for Cross-Core Communication. IPDPS 2021: 182-191 - [c99]Erika S. Alcorta, Andreas Gerstlauer:
Learning-Based Workload Phase Classification and Prediction Using Performance Monitoring Counters. MLCAD 2021: 1-6 - [c98]Ahsan Saeed, Daniel Mueller-Gritschneder, Falk Rehm, Arne Hamann, Dirk Ziegenbein, Ulf Schlichtmann, Andreas Gerstlauer:
Learning based Memory Interference Prediction for Co-running Applications on Multi-Cores. MLCAD 2021: 1-6 - [c97]Erika S. Alcorta, Pranav Rama, Aswin Ramachandran, Andreas Gerstlauer:
Phase-Aware CPU Workload Forecasting. SAMOS 2021: 195-209 - [i6]Jackson Farley, Andreas Gerstlauer:
Memory-Aware Fusing and Tiling of Neural Networks for Accelerated Edge Inference. CoRR abs/2107.06960 (2021) - [i5]Eva Darulova, Babak Falsafi, Andreas Gerstlauer, Phillip Stanley-Marbell:
Approximate Systems (Dagstuhl Seminar 21302). Dagstuhl Reports 11(6): 147-163 (2021) - 2020
- [j27]Sami Salamin, Martin Rapp, Jörg Henkel, Andreas Gerstlauer, Hussam Amrouch:
Dynamic Power and Energy Management for NCFET-Based Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3361-3372 (2020) - [j26]Heesu Kim, Jongho Kim, Hussam Amrouch, Jörg Henkel, Andreas Gerstlauer, Kiyoung Choi, Hanmin Park:
Aging Compensation With Dynamic Computation Approximation. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(4): 1319-1332 (2020) - [j25]Zhuoran Zhao, Kamyar Mirzazad Barijough, Andreas Gerstlauer:
Network-level Design Space Exploration of Resource-constrained Networks-of-Systems. ACM Trans. Embed. Comput. Syst. 19(4): 22:1-22:26 (2020) - [c96]Kishore Punniyamurthy, Andreas Gerstlauer:
TAFE: Thread Address Footprint Estimation for Capturing Data/Thread Locality in GPU Systems. PACT 2020: 17-29 - [c95]Sami Salamin, Martin Rapp, Hussam Amrouch, Andreas Gerstlauer, Jörg Henkel:
Energy Optimization in NCFET-based Processors. DATE 2020: 630-633 - [c94]Tanfer Alan, Andreas Gerstlauer, Jörg Henkel:
Runtime Accuracy-Configurable Approximate Hardware Synthesis Using Logic Gating and Relaxation. DATE 2020: 1578-1581 - [c93]Mochamad Asri, Curtis Dunham, Roxana Rusitoru, Andreas Gerstlauer, Jonathan Beard:
The Non-Uniform Compute Device (NUCD) Architecture for Lightweight Accelerator Offload. PDP 2020: 38-45 - [c92]Kishore Punniyamurthy, Andreas Gerstlauer:
Off-Chip Congestion Management for GPU-based Non-Uniform Processing-in-Memory Networks. PDP 2020: 282-289 - [c91]Kishore Punniyamurthy, Shomit Das, Andreas Gerstlauer:
Cacheline Utilization-Aware Link Traffic Compression for Modular GPUs. VLSID 2020: 137-142 - [e5]Tulika Mitra, Andreas Gerstlauer:
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2020, Singapore, September 20-25, 2020. IEEE 2020, ISBN 978-1-7281-9192-8 [contents] - [e4]Tulika Mitra, Andreas Gerstlauer:
20th International Conference on Embedded Software, EMSOFT 2020, Singapore, September 20-25, 2020. IEEE 2020, ISBN 978-1-7281-9195-9 [contents] - [i4]Qinzhe Wu, Jonathan Beard, Ashen Ekanayake, Andreas Gerstlauer, Lizy K. John:
Virtual-Link: A Scalable Multi-Producer, Multi-Consumer Message Queue Architecture for Cross-Core Communication. CoRR abs/2012.05181 (2020)
2010 – 2019
- 2019
- [j24]Hussam Amrouch, Seyed Borna Ehsani, Andreas Gerstlauer, Jörg Henkel:
On the Efficiency of Voltage Overscaling under Temperature and Aging Effects. IEEE Trans. Computers 68(11): 1647-1662 (2019) - [j23]Kamyar Mirzazad Barijough, Zhuoran Zhao, Andreas Gerstlauer:
Quality/Latency-Aware Real-time Scheduling of Distributed Streaming IoT Applications. ACM Trans. Embed. Comput. Syst. 18(5s): 83:1-83:23 (2019) - [c90]Shijia Wei, Aydin Aysu, Michael Orshansky, Andreas Gerstlauer, Mohit Tiwari:
Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems. HOST 2019: 111-120 - [c89]Jongho Kim, Heesu Kim, Hussam Amrouch, Jörg Henkel, Andreas Gerstlauer, Kiyoung Choi:
Aging Gracefully with Approximation. ISCAS 2019: 1-5 - [c88]Rafael Stahl, Zhuoran Zhao, Daniel Mueller-Gritschneder, Andreas Gerstlauer, Ulf Schlichtmann:
Fully Distributed Deep Learning Inference on Resource-Constrained Edge Devices. SAMOS 2019: 77-90 - [c87]Ahmed Abdelhadi, Andreas Gerstlauer, Sriram Vishwanath:
Real-Time Rate Distortion Optimized and Adaptive Low Complexity Algorithms for Video Streaming. SysCon 2019: 1-8 - [c86]Ahmed Abdelhadi, Andreas Gerstlauer, Sriram Vishwanath:
Horus Testbed: Implementation of Real-Time Video Streaming Protocols. SysCon 2019: 1-8 - [c85]Joseph Whitehouse, Qinzhe Wu, Shuang Song, Eugene John, Andreas Gerstlauer, Lizy K. John:
A Study of Core Utilization and Residency in Heterogeneous Smart Phone Architectures. ICPE 2019: 67-78 - [p5]Seogoo Lee, Andreas Gerstlauer:
Approximate High-Level Synthesis of Custom Hardware. Approximate Circuits 2019: 205-223 - 2018
- [j22]Seogoo Lee, Andreas Gerstlauer:
Data-Dependent Loop Approximations for Performance-Quality Driven High-Level Synthesis. IEEE Embed. Syst. Lett. 10(1): 18-21 (2018) - [j21]Shuang Song, Xu Liu, Qinzhe Wu, Andreas Gerstlauer, Tao Li, Lizy K. John:
Start Late or Finish Early: A Distributed Graph Processing System with Redundancy Reduction. Proc. VLDB Endow. 12(2): 154-168 (2018) - [j20]Zhuoran Zhao, Kamyar Mirzazad Barijough, Andreas Gerstlauer:
DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained IoT Edge Clusters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2348-2359 (2018) - [j19]Dongwook Lee, Andreas Gerstlauer:
Learning-Based, Fine-Grain Power Modeling of System-Level Hardware IPs. ACM Trans. Design Autom. Electr. Syst. 23(3): 30:1-30:25 (2018) - [c84]Wooseok Lee, Reena Panda, Dam Sunwoo, José A. Joao, Andreas Gerstlauer, Lizy K. John:
BUQS: Battery- and user-aware QoS scaling for interactive mobile devices. ASP-DAC 2018: 64-69 - [c83]Reena Panda, Xinnian Zheng, Andreas Gerstlauer, Lizy Kurian John:
CAMP: Accurate modeling of core and memory locality for proxy generation of big-data applications. DATE 2018: 337-342 - [c82]Aydin Aysu, Youssef Tobah, Mohit Tiwari, Andreas Gerstlauer, Michael Orshansky:
Horizontal side-channel vulnerabilities of post-quantum key exchange protocols. HOST 2018: 81-88 - [c81]Behzad Boroujerdian, Hussam Amrouch, Jörg Henkel, Andreas Gerstlauer:
Trading Off Temperature Guardbands via Adaptive Approximations. ICCD 2018: 202-209 - [c80]Wenxiao Yu, Jacob Kornerup, Andreas Gerstlauer:
MASES: Mobility And Slack Enhanced Scheduling For Latency-Optimized Pipelined Dataflow Graphs. SCOPES 2018: 104-109 - [i3]Shuang Song, Xu Liu, Qinzhe Wu, Andreas Gerstlauer, Tao Li, Lizy K. John:
Start Late or Finish Early: A Distributed Graph Processing System with Redundancy Reduction. CoRR abs/1805.12305 (2018) - [i2]Phillip Stanley-Marbell, Armin Alaghi, Michael Carbin, Eva Darulova, Lara Dolecek, Andreas Gerstlauer, Ghayoor Gillani, Djordje Jevdjic, Thierry Moreau, Mattia Cacciotti, Alexandros Daglis, Natalie D. Enright Jerger, Babak Falsafi, Sasa Misailovic, Adrian Sampson, Damien Zufferey:
Exploiting Errors for Efficiency: A Survey from Circuits to Algorithms. CoRR abs/1809.05859 (2018) - 2017
- [j18]Sabine Francis, Andreas Gerstlauer:
A Reactive and Adaptive Data Flow Model for Network-of-System Specification. IEEE Embed. Syst. Lett. 9(4): 121-124 (2017) - [j17]Guillermo Payá-Vayá, Andreas Gerstlauer:
Guest Editorial: Special Issue on the 2015 International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation (SAMOS XV). Int. J. Parallel Program. 45(6): 1417-1419 (2017) - [j16]Xinnian Zheng, Lizy K. John, Andreas Gerstlauer:
LACross: Learning-Based Analytical Cross-Platform Performance and Power Prediction. Int. J. Parallel Program. 45(6): 1488-1514 (2017) - [j15]Zhuoran Zhao, Andreas Gerstlauer, Lizy K. John:
Source-Level Performance, Energy, Reliability, Power and Thermal (PERPT) Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(2): 299-312 (2017) - [c79]Hussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, Jörg Henkel:
Towards Aging-Induced Approximations. DAC 2017: 41:1-41:6 - [c78]Reena Panda, Xinnian Zheng, Jiajun Wang, Andreas Gerstlauer, Lizy K. John:
Statistical Pattern Based Modeling of GPU Memory Access Streams. DAC 2017: 81:1-81:6 - [c77]Kishore Punniyamurthy, Behzad Boroujerdian, Andreas Gerstlauer:
GATSim: Abstract timing simulation of GPUs. DATE 2017: 43-48 - [c76]Seogoo Lee, Lizy K. John, Andreas Gerstlauer:
High-level synthesis of approximate hardware under joint precision and voltage scaling. DATE 2017: 187-192 - [c75]Xinnian Zheng, Haris Vikalo, Shuang Song, Lizy K. John, Andreas Gerstlauer:
Sampling-based binary-level cross-platform performance estimation. DATE 2017: 1709-1714 - [c74]Shuang Song, Raj Desikan, Mohamad Barakat, Sridhar Sundaram, Andreas Gerstlauer, Lizy K. John:
Fine-Grain Program Snippets Generator for Mobile Core Design. ACM Great Lakes Symposium on VLSI 2017: 245-250 - [c73]Wooseok Lee, Dam Sunwoo, Christopher D. Emmons, Andreas Gerstlauer, Lizy K. John:
Exploring Heterogeneous-ISA Core Architectures for High-Performance and Energy-Efficient Mobile SoCs. ACM Great Lakes Symposium on VLSI 2017: 419-422 - [c72]Maithili P. Gandhe, Lizy K. John, Andreas Gerstlauer:
POWSER: A novel user-experience based power management metric. IGSC 2017: 1-8 - [c71]Wooseok Lee, Dam Sunwoo, Andreas Gerstlauer, Lizy K. John:
Cloud-Guided QoS and Energy Management for Mobile Interactive Web Applications. MOBILESoft@ICSE 2017: 25-29 - [c70]Zhuoran Zhao, Vasileios Tsoutsouras, Dimitrios Soudris, Andreas Gerstlauer:
Network/system co-simulation for design space exploration of IoT applications. SAMOS 2017: 46-53 - [p4]Soonhoi Ha, Jürgen Teich, Christian Haubelt, Michael Glaß, Tulika Mitra, Rainer Dömer, Petru Eles, Aviral Shrivastava, Andreas Gerstlauer, Shuvra S. Bhattacharyya:
Introduction to Hardware/Software Codesign. Handbook of Hardware/Software Codesign 2017: 3-26 - [p3]Daniel Mueller-Gritschneder, Andreas Gerstlauer:
Host-Compiled Simulation. Handbook of Hardware/Software Codesign 2017: 593-619 - [p2]Gunar Schirner, Andreas Gerstlauer, Rainer Dömer:
SCE: System-on-Chip Environment. Handbook of Hardware/Software Codesign 2017: 1019-1050 - 2016
- [c69]Shuang Song, Xinnian Zheng, Andreas Gerstlauer, Lizy K. John:
Fine-grained power analysis of emerging graph processing workloads for cloud operations management. IEEE BigData 2016: 2121-2126 - [c68]Xinnian Zheng, Lizy K. John, Andreas Gerstlauer:
Accurate phase-level cross-platform power and performance estimation. DAC 2016: 4:1-4:6 - [c67]Hussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, Jörg Henkel:
Reliability-aware design to suppress aging. DAC 2016: 12:1-12:6 - [c66]Shuang Song, Meng Li, Xinnian Zheng, Michael LeBeane, Jee Ho Ryoo, Reena Panda, Andreas Gerstlauer, Lizy K. John:
Proxy-Guided Load Balancing of Graph Processing Workloads on Heterogeneous Clusters. ICPP 2016: 77-86 - [c65]Jiajun Wang, Ahmed Khawaja, George Biros, Andreas Gerstlauer, Lizy K. John:
Optimizing GPGPU Kernel Summation for Performance and Energy Efficiency. ICPP Workshops 2016: 123-132 - [c64]Seogoo Lee, Dongwook Lee, Kyungtae Han, Emily Shriver, Lizy K. John, Andreas Gerstlauer:
Statistical quality modeling of approximate hardware. ISQED 2016: 163-168 - [c63]Mochamad Asri, Ardavan Pedram, Lizy K. John, Andreas Gerstlauer:
Simulator calibration for accelerator-rich architecture studies. SAMOS 2016: 88-95 - [c62]Reena Panda, Xinnian Zheng, Shuang Song, Jee Ho Ryoo, Michael LeBeane, Andreas Gerstlauer, Lizy K. John:
Genesys: Automatically generating representative training sets for predictive benchmarking. SAMOS 2016: 116-123 - [c61]Dylan Pfeifer, Andreas Gerstlauer, Jonathan Valvano:
Adaptive resolution control in distributed cyber-physical system simulation. WSC 2016: 1487-1498 - [e3]Walid A. Najjar, Andreas Gerstlauer:
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016, Agios Konstantinos, Samos Island, Greece, July 17-21, 2016. IEEE 2016, ISBN 978-1-5090-3076-7 [contents] - 2015
- [j14]Seogoo Lee, Andreas Gerstlauer, Robert W. Heath Jr.:
Distributed Real-Time Implementation of Interference Alignment with Analog Feedback. IEEE Trans. Veh. Technol. 64(8): 3513-3525 (2015) - [c60]Dongwook Lee, Lizy K. John, Andreas Gerstlauer:
Dynamic power and performance back-annotation for fast and accurate functional hardware simulation. DATE 2015: 1126-1131 - [c59]Oliver Bringmann, Wolfgang Ecker, Andreas Gerstlauer, Ajay Goyal, Daniel Mueller-Gritschneder, Prasanth Sasidharan, Simranjit Singh:
The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems. DATE 2015: 1698-1707 - [c58]Dongwook Lee, Taemin Kim, Kyungtae Han, Yatin Hoskote, Lizy K. John, Andreas Gerstlauer:
Learning-Based Power Modeling of System-Level Black-Box IPs. ICCAD 2015: 847-853 - [c57]Wooseok Lee, Youngchun Kim, Jee Ho Ryoo, Dam Sunwoo, Andreas Gerstlauer, Lizy K. John:
PowerTrain: A learning-based calibration of McPAT power models. ISLPED 2015: 189-194 - [c56]Xinnian Zheng, Pradeep Ravikumar, Lizy K. John, Andreas Gerstlauer:
Learning-based analytical cross-platform performance prediction. SAMOS 2015: 52-59 - [e2]Gabriela Nicolescu, Andreas Gerstlauer:
2015 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015, Amsterdam, Netherlands, October 4-9, 2015. IEEE 2015, ISBN 978-1-4673-8321-9 [contents] - 2014
- [j13]Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn:
Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator. IEEE Trans. Computers 63(8): 1854-1867 (2014) - [j12]Parisa Razaghi, Andreas Gerstlauer:
Host-Compiled Multicore System Simulation for Early Real-Time Performance Evaluation. ACM Trans. Embed. Comput. Syst. 13(5s): 166:1-166:26 (2014) - [j11]Ardavan Pedram, John D. McCalpin, Andreas Gerstlauer:
A Highly Efficient Multicore Floating-Point FFT Architecture Based on Hybrid Linear Algebra/FFT Cores. J. Signal Process. Syst. 77(1-2): 169-190 (2014) - [c55]Jin Miao, Andreas Gerstlauer, Michael Orshansky:
Multi-level approximate logic synthesis under general error constraints. ICCAD 2014: 504-510 - [c54]Ahmed Khawaja, Jiajun Wang, Andreas Gerstlauer, Lizy K. John, Dhairya Malhotra, George Biros:
Performance analysis of HPC applications with irregular tree data structures. ICPADS 2014: 418-425 - [c53]Darshan Gandhi, Andreas Gerstlauer, Lizy K. John:
FastSpot: Host-compiled thermal estimation for early design space exploration. ISQED 2014: 625-632 - [i1]Ahmed Abdel-Hadi, Andreas Gerstlauer, Sriram Vishwanath:
Real-Time Rate-Distortion Optimized Streaming of Wireless Video. CoRR abs/1406.1915 (2014) - 2013
- [j10]Dylan Pfeifer, Jonathan Valvano, Andreas Gerstlauer:
SimConnect and SimTalk for distributed cyber-physical system simulation. Simul. 89(10): 1254-1271 (2013) - [j9]Ku He, Andreas Gerstlauer, Michael Orshansky:
Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems. IEEE Trans. Circuits Syst. Video Technol. 23(6): 961-974 (2013) - [c52]Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn:
Floating Point Architecture Extensions for Optimized Matrix Factorization. IEEE Symposium on Computer Arithmetic 2013: 49-58 - [c51]Hyungman Park, Andreas Gerstlauer:
Toward a fast stochastic simulation processor for biochemical reaction networks. ASAP 2013: 50-58 - [c50]Ardavan Pedram, John D. McCalpin, Andreas Gerstlauer:
Transforming a linear algebra core to an FFT accelerator. ASAP 2013: 175-184 - [c49]Suhas Chakravarty, Zhuoran Zhao, Andreas Gerstlauer:
Automated, retargetable back-annotation for host compiled performance and power modeling. CODES+ISSS 2013: 36:1-36:10 - [c48]Jin Miao, Andreas Gerstlauer, Michael Orshansky:
Approximate logic synthesis under general error magnitude and frequency constraints. ICCAD 2013: 779-786 - [c47]Artur Mariano, Dongwook Lee, Andreas Gerstlauer, Derek Chiou:
Hardware and Software Implementations of Prim's Algorithm for Efficient Minimum Spanning Tree Computation. IESS 2013: 151-158 - [c46]Ku He, Andreas Gerstlauer, Michael Orshansky:
Low-energy digital filter design based on controlled timing error acceptance. ISQED 2013: 151-157 - [c45]Dylan Pfeifer, Andreas Gerstlauer, Jonathan Valvano:
Dynamic resolution in distributed cyber-physical system simulation. SIGSIM-PADS 2013: 277-284 - [c44]Seogoo Lee, Andreas Gerstlauer:
Fine Grain Precision Scaling for Datapath Approximations in Digital Signal Processing Systems. VLSI-SoC (Selected Papers) 2013: 119-143 - [c43]Seogoo Lee, Andreas Gerstlauer:
Fine grain word length optimization for dynamic precision scaling in DSP systems. VLSI-SoC 2013: 266-271 - 2012
- [j8]Parisa Razaghi, Andreas Gerstlauer:
Predictive OS Modeling for Host-Compiled Simulation of Periodic Real-Time Task Sets. IEEE Embed. Syst. Lett. 4(1): 5-8 (2012) - [j7]Ardavan Pedram, Robert A. van de Geijn, Andreas Gerstlauer:
Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures. IEEE Trans. Computers 61(12): 1724-1736 (2012) - [j6]Jing Lin, Andreas Gerstlauer, Brian L. Evans:
Communication-aware Heterogeneous Multiprocessor Mapping for Real-time Streaming Systems. J. Signal Process. Syst. 69(3): 279-291 (2012) - [c42]Jackson W. Massey, Jonathan Starr, Seogoo Lee, Dongwook Lee, Andreas Gerstlauer, Robert W. Heath Jr.:
Implementation of a real-time wireless interference alignment network. ACSCC 2012: 104-108 - [c41]Ardavan Pedram, Syed Zohaib Gilani, Nam Sung Kim, Robert A. van de Geijn, Michael J. Schulte, Andreas Gerstlauer:
A Linear Algebra Core Design for Efficient Level-3 BLAS. ASAP 2012: 149-152 - [c40]Andreas Gerstlauer, Suhas Chakravarty, Manan Kathuria, Parisa Razaghi:
Abstract system-level models for early performance and power exploration. ASP-DAC 2012: 213-218 - [c39]Parisa Razaghi, Andreas Gerstlauer:
Automatic timing granularity adjustment for host-compiled software simulation. ASP-DAC 2012: 567-572 - [c38]Dongwook Lee, Hyungman Park, Andreas Gerstlauer:
Synthesis of optimized hardware transactors from abstract communication specifications. CODES+ISSS 2012: 403-412 - [c37]Jin Miao, Ku He, Andreas Gerstlauer, Michael Orshansky:
Modeling and synthesis of quality-energy optimal approximate adders. ICCAD 2012: 728-735 - [c36]Ku He, Andreas Gerstlauer, Michael Orshansky:
Low-energy signal processing using circuit-level timing-error acceptance. ICICDT 2012: 1-4 - [c35]Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn:
On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators. SBAC-PAD 2012: 19-26 - 2011
- [c34]Ardavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn:
A high-performance, low-power linear algebra core. ASAP 2011: 35-42 - [c33]Rainer Dömer, Weiwei Chen, Xu Han, Andreas Gerstlauer:
Multi-core parallel simulation of System-level Description Languages. ASP-DAC 2011: 311-316 - [c32]Parisa Razaghi, Andreas Gerstlauer:
Host-compiled multicore RTOS simulator for embedded real-time software development. DATE 2011: 222-227 - [c31]Ku He, Andreas Gerstlauer, Michael Orshansky:
Controlled timing-error acceptance for low energy IDCT design. DATE 2011: 758-763 - [c30]Dylan Pfeifer, Andreas Gerstlauer:
Expression-Level Parallelism for Distributed Spice Circuit Simulation. DS-RT 2011: 12-17 - [c29]Martha Salome Lopez, Andreas Gerstlauer, Alfonso Ávila, Sergio Omar Martinez-Chapa:
A programmable and configurable multi-port System-on-Chip for stimulating electrokinetically-driven microfluidic devices. EMBC 2011: 8361-8364 - [c28]Jing Lin, Akshaya Srivatsa, Andreas Gerstlauer, Brian L. Evans:
Heterogeneous multiprocessor mapping for real-time streaming systems. ICASSP 2011: 1605-1608 - [c27]Ahmed Abdel-Hadi, Jonas Michel, Andreas Gerstlauer, Sriram Vishwanath:
Real-Time Optimization of Video Transmission in a Network of AAVs. VTC Fall 2011: 1-5 - 2010
- [j5]Gunar Schirner, Andreas Gerstlauer, Rainer Dömer:
Fast and accurate processor models for efficient MPSoC design. ACM Trans. Design Autom. Electr. Syst. 15(2): 10:1-10:26 (2010) - [c26]Andreas Gerstlauer, Gunar Schirner:
Platform modeling for exploration and synthesis. ASP-DAC 2010: 725-731 - [c25]Gunar Schirner, Andreas Gerstlauer, Rainer Dömer:
System-level development of embedded software. ASP-DAC 2010: 903-909 - [c24]Andreas Gerstlauer:
Host-compiled simulation of multi-core platforms. International Symposium on Rapid System Prototyping 2010: 1-6 - [c23]Andreas Gerstlauer:
Host-compiled simulation of multi-core platforms. International Symposium on Rapid System Prototyping 2010: 1-6 - [c22]Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubühr, Jürgen Teich:
A system-level synthesis approach from formal application models to generic bus-based MPSoCs. ICSAMOS 2010: 118-125
2000 – 2009
- 2009
- [j4]Andreas Gerstlauer, Christian Haubelt, Andy D. Pimentel, Todor P. Stefanov, Daniel D. Gajski, Jürgen Teich:
Electronic System-Level Synthesis Methodologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1517-1530 (2009) - [c21]Rainer Dömer, Andreas Gerstlauer, Wolfgang Müller:
Introduction to hardware-dependent software design hardware-dependent software for multi- and many-core embedded systems. ASP-DAC 2009: 290-292 - [c20]Amal Banerjee, Andreas Gerstlauer:
Transaction Level Modeling of Best-Effort Channels for Networked Embedded Devices. IESS 2009: 77-88 - [c19]Ardavan Pedram, David Craven, Andreas Gerstlauer:
Modeling Cache Effects at the Transaction Level. IESS 2009: 89-101 - 2008
- [j3]Rainer Dömer, Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Lukai Cai, Haobo Yu, Samar Abdi, Daniel D. Gajski:
System-on-Chip Environment: A SpecC-Based Framework for Heterogeneous MPSoC Design. EURASIP J. Embed. Syst. 2008 (2008) - [j2]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski:
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 466-475 (2008) - [c18]Gunar Schirner, Andreas Gerstlauer, Rainer Dömer:
Automatic generation of hardware dependent software for MPSoCs from abstract system specifications. ASP-DAC 2008: 271-276 - [c17]Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Daniel Gajski, Atsushi Nakamura, Dai Araki, Yuuji Nishihara:
Specify-explore-refine (SER): from specification to implementation. DAC 2008: 586-591 - 2007
- [j1]Andreas Gerstlauer, Dongwan Shin, Junyu Peng, Rainer Dömer, Daniel Gajski:
Automatic Layer-Based Generation of System-On-Chip Bus Communication Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1676-1687 (2007) - [c16]Gunar Schirner, Andreas Gerstlauer, Rainer Dömer:
Abstract, Multifaceted Modeling of Embedded Processors for System Level Design. ASP-DAC 2007: 384-389 - [c15]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
An Interactive Design Environment for C-based High-Level Synthesis. IESS 2007: 135-144 - [c14]Gunar Schirner, Gautam Sachdeva, Andreas Gerstlauer, Rainer Dömer:
Embedded Software Development in a System-Level Design Flow. IESS 2007: 289-298 - [e1]Achim Rettberg, Mauro Cesar Zanella, Rainer Dömer, Andreas Gerstlauer, Franz-Josef Rammig:
Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30 - June 1, 2007, Irvine, CA, USA. IFIP Advances in Information and Communication Technology 231, Springer 2007, ISBN 978-0-387-72257-3 [contents] - 2006
- [c13]Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rainer Dömer, Daniel D. Gajski:
Automatic generation of transaction level models for rapid design space exploration. CODES+ISSS 2006: 64-69 - 2005
- [c12]Andreas Gerstlauer, Dongwan Shin, Rainer Dömer, Daniel D. Gajski:
System-level communication modeling for network-on-chip synthesis. ASP-DAC 2005: 45-48 - [c11]Lukai Cai, Andreas Gerstlauer, Daniel Gajski:
Multi-metric and multi-entity characterization of applications for early system design exploration. ASP-DAC 2005: 944-947 - [c10]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
Automatic network generation for system-on-chip communication design. CODES+ISSS 2005: 255-260 - [c9]Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski:
Automatic Generation of Communication Architectures. IESS 2005: 179-188 - 2004
- [c8]Lukai Cai, Andreas Gerstlauer, Daniel Gajski:
Retargetable profiling for rapid, early system-level design space exploration. DAC 2004: 281-286 - 2003
- [c7]Haobo Yu, Andreas Gerstlauer, Daniel Gajski:
RTOS scheduling in transaction level models. CODES+ISSS 2003: 31-36 - [c6]Andreas Gerstlauer, Haobo Yu, Daniel Gajski:
RTOS Modeling for System Level Design. DATE 2003: 10130-10135 - [p1]Andreas Gerstlauer, Haobo Yu, Daniel D. Gajski:
RTOS Modeling for System Level Design. Embedded Software for SoC 2003: 55-68 - 2002
- [c5]Slim Ben Saoud, Daniel D. Gajski, Andreas Gerstlauer:
Co-design of embedded controllers for power electronics and electric systems. ISIC 2002: 379-383 - [c4]Rainer Dömer, Andreas Gerstlauer, Wolfgang Müller:
The Formal Execution Semantics of SpecC. ISSS 2002: 150-155 - [c3]Daniel Gajski, Andreas Gerstlauer:
System-Level Abstraction Semantics. ISSS 2002: 231-236 - [c2]Slim Ben Saoud, Daniel D. Gajski, Andreas Gerstlauer:
Seamless approach for the design of control systems for power electronics and electric drives. SMC 2002: 6 - 2001
- [b1]Andreas Gerstlauer, Rainer Dömer, Junyu Peng, Daniel D. Gajski:
System Design - A Practical Guide with SpecC. Springer 2001, ISBN 978-0-7923-7387-2, pp. 1-255 - 2000
- [c1]Achim Rettberg, Franz J. Rammig, Andreas Gerstlauer, Daniel Gajski, Wolfram Hardt, Bernd Kleinjohann:
The Specification Language SpecC within the PARADISE Design Environment. DIPES 2000: 111-120
Coauthor Index
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