pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Common SystemVerilog components
RISC-V Debug Support for our PULP RISC-V Cores
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
A minimal GPU design in Verilog to learn how GPUs work from the ground up