Chandrakanth Lakshminarayana

AXI is a multi channel bus which is popularly used as an interfacing protocol between multiple IP's and is useful both in RTL design and ASIC Verification. Below are the key concepts which are needed to understand AXI protocol in depth. [1] Difference between AXI and AHB. Number of Channels used in AXI. Why there is no separate Read response on AXI. [2] What are out of order and outstanding transaction in AXI. [3] What is the address boundary that slave can access in AXI. [4] Transfer mechanism for Write / Read with / without delay. [5] Valid and Ready hand shaking mechanism. What is deadlock condition. How to overcome it. [6] Difference b/w Incrementing and Wrapping Burst. What is a Fixed Burst type. [7] Difference b/w Bufferable and Cacheable type of transaction in AXI. [8] Complete understanding of Exclusive access phenomenon. Difference b/w OKAY and EXOKAY response. [9] What is a Locked access in AXI3. Why it is removed in AXI4. [10] What are the conditions for SLVERR and DECERR. [11] What is a QOS support for AXI4. What are the significance of AxREGION and AxUSER in AXI4. [12] Difference b/w AXI3 and AXI4. [13] What is a write interleaving method in AXI3 and why it's removed in AXI4. #vlsi #asic #semiconductorindustry #electricalengineering

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🚨 **Ensuring Proper PG Bias Off State in IC Designs Using Synopsys VSLP Tool** 🚨 In Integrated Circuit (IC) design, managing power gating bias off states correctly is crucial for optimizing power efficiency and ensuring reliable operation. The Synopsys VSLP tool is essential for detecting and resolving pg_biasoff_state issues. Here’s a concise overview of what pg_biasoff_state entails and its importance. ### **What is PG Bias Off State?** **PG Bias Off State** refers to the condition where biasing of power-gated domains is correctly turned off to save power. Ensuring this state is properly managed is vital for achieving power efficiency and maintaining functional integrity. ### **Importance of Addressing PG Bias Off State Violations** - **Power Efficiency**: Proper management of bias off states reduces power consumption, enhancing the overall energy efficiency of the IC. - **Functional Integrity**: Correctly handling bias off states ensures that power-gated domains are fully powered down without unintended leakage or partial functionality. - **Reliability**: Ensuring proper bias off states enhances the reliability and stability of the IC, preventing potential issues from partial biasing. - **Thermal Management**: Reducing power consumption through effective bias off state management helps in thermal management by lowering heat generation. ### **Detecting and Addressing PG Bias Off State Violations with Synopsys VSLP** The Synopsys VSLP tool provides advanced capabilities to detect and rectify issues related to PG bias off states, ensuring robust and reliable IC designs. #### **1. Static Analysis** - **Bias Off State Checks**: Analyze the design to ensure that power-gated domains are correctly biased off when required. - **State Transition Verification**: Verify that transitions to and from the bias off state are managed correctly, preventing unintended power leakage. #### **2. Dynamic Simulation** - **Power Down Scenarios**: Simulate various power down scenarios to assess the impact on system functionality and ensure proper bias off state management. - **Power Consumption Analysis**: Monitor power consumption during bias off states to identify any irregularities or inefficiencies. ### **Best Practices for Managing PG Bias Off States** 1. **Clear Power Management Strategy**: Develop a clear strategy for managing bias off states, including guidelines for when and how components should enter and exit these states. 2. **Continuous Validation**: Regularly validate bias off state implementation throughout the design process to catch and address issues early. 3. **Collaborative Approach**: Work closely with power management and system design teams to ensure that bias off states are integrated seamlessly into the overall design. 4. **Advanced Tool Utilization**: Use advanced tools like Synopsys VSLP for automated detection and correction of bias off state issues. #workwithuppula #synopsys #VSLPTool #powerefficiency Thanks, Vishnu

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Just a thought RTL Design has few logics which is not required as per the design specifications, this portion of code gets excluded in code coverage analysis. By knowing this fact we still synthesis the logic and it increases the gate counts. but functionaly this logic has no use. Now can this be a area for AI based tool to discard that portion of logic during synthesis and we reduce the gate count?

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© Topic: VLSI Glossary © ⏭ ⏭⏭ ⏭ GrowVLSI ⏮ ⏮ ⏮ ⏮ (A-S posted few days back) T: TB- Tera Byte TN- Technology Node TG- Transmission Gate TTL- Transistor Transistor Logic TT- Typical Typical (TT is the corner where both NMOS and PMOS are typical, when this corner is enabled the processing parameters may be typical/hard because corner analysis does include all the process variation possiblities ) TCL- Tool Command Language TF- Technology File 😍It is an ASCII file in which information about all the metal layers, vias and their design rules are available😍 TLU+: Timing Library Update/Table LookUp 😍 TLU+ file provides RC parasitic information of metal per unit length which is used to calculate the net delay. All TLU+ file data is completely technology dependent and is given by Foundry 😍 TNS- Total Negative Slack U: ULVT- Ultra Low Threshold Voltage UPF- Unified Power Format ULSI- Ultra Large Scale Integration V: VLSI- Very Large Scale Integration VHDL- VHSIC(Very High Speed Integrated Circuit) Hardware Descriptive Language W: WNS- Worst Negative Slack X, Y, Z: Didnot find anything Content Writer B. Lokeshwar

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Recently, Apple has launched the iPhone 16 series, enabling WiFi 7 for iPhone users. Let us do some brief system-level calculations to understand noise and ADC requirements.   Assumptions: Modulation Scheme: 4096-QAM Channel Bandwidth: 320 MHz Received Power (P_RX): -50 dBm Front-end RX Gain ( G ): 25 dB Front-end Noise Figure ( NF ): 10 dB Thermal Noise Power Density ( N_0 ): -174 dBm/Hz Step 1: Thermal Noise Power Calculation The noise power density is a function of thermal noise at room temperature (290K). Given the bandwidth B = 320 MHz, the total noise power over the bandwidth is: N_total = N_0 + 10log10(B) N_total = -174 + 85.05 = -88.95 dBm Step 2: Adjust for Noise Figure by Front End The receiver’s noise figure (NF) adds noise to the system. Adjust the total noise power by the noise figure: N_output = N_total + NF N_output = -88.95 dBm + 10 dB = -78.95 dBm This represents the total noise power at the output of the front end. Step 3: Signal Power at the ADC Input The signal power at the input of the ADC is the received power amplified by the front-end gain (G = 25 dB). P_ADC_in = -50 dBm + 25 dB = -25 dBm Step 4: Signal-to-Noise Ratio (SNR) Calculation The SNR at the ADC is the difference between the signal power at the ADC input and the total noise power at the output: SNR = P_ADC_in – N_output SNR = -25 dBm - (-78.95 dBm) = 53.95 dB This is the SNR at the input of the ADC. Step 5: Determine the ADC Resolution (ENOB) The effective number of bits (ENOB) of the ADC can be determined from the SNR using the relation: SNR = 6.02 x ENOB + 1.76 dB ENOB = (SNR - 1.76) / 6.02 ENOB = (53.95 - 1.76) / 6.02 = 8.67 bits Step 6: Verify SNR Requirement for 4096-QAM For 4096-QAM, the required SNR can be approximated by: SNR_required = 10log10(M), where M = 4096 for 4096-QAM SNR_required = 10log10(4096) = 36 dB Since the calculated SNR at the ADC input (53.95 dB) exceeds the required SNR for 4096-QAM (36 dB), the system is well within the acceptable range for decoding the signal. Step 7: ADC Full-Scale Dynamic Range To ensure proper ADC operation, the full-scale range of the ADC should encompass both the noise floor and the signal power. The total noise power at the ADC input: N_output = -78.95 dBm The signal power at the ADC input: P_ADC_in = -25 dBm Thus, the required dynamic range (difference between the signal and noise) is: Dynamic Range = P_ADC_in – N_output = -25 - (-78.95) = 53.95 dB The ENOB of 8.67 bits corresponds to a dynamic range DR = 6.02 x 8.67 = 52.2 dB This is close to the 53.95 dB SNR at the input of the ADC. Conclusion: For a typical WiFi 7 system with 4096-QAM and 320 MHz bandwidth: Required ADC ENOB: 8.67 bits. However, a nominal ADC resolution of 10 bits would provide adequate performance with design margins for implementation losses, ensuring the system can properly digitize the incoming signal. *Please note that Front End gain is a variable that also plays a crucial role in properly functioning WiFi Receiver.

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Semiconductors are the backbone of modern technology, but have you heard about VLSI? Prepare to be amazed by the evolution of telecom industry with #TechFacts⚡️ Department of Telecommunications ( DOT ) #didyouknowfacts #facts #semiconductors #vlsi #telecom

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Hello Connections Click on the below link to understand PCIe Config Space and visit the channel to see other videos related to PCIe protocol. Subscribe to my YouTube channel for more such informative videos. https://lnkd.in/grYJmusS

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#fundamentalseries UVM Monitor Classes 7. uvm_monitor * Observes DUT signals and converts them into transactions. * Sends transactions to other components like scoreboards and coverage collectors. * Passive component, does not drive signals. Environment Classes 8. uvm_env * Container class for grouping related UVM components (e.g., agents, scoreboards). * Typically represents a complete verification environment for a specific DUT. Agent Classes 9. uvm_agent * Groups related driver, sequencer, and monitor components. * Can be active (contains a driver and sequencer) or passive (contains only a monitor). Reporting Classes 10. uvm_report_object * Provides reporting utilities for printing messages, warnings, and errors. * Base class for components that need reporting capabilities. 11. uvm_report_server * Centralized reporting mechanism. * Collects and processes messages from uvm_report_object instances. Scoreboard and Analysis Classes 12. uvm_scoreboard * Analyzes DUT outputs and compares them with expected results. * Receives transactions from monitors via analysis ports. 13. uvm_analysis_port * Used for broadcasting transactions to one or more analysis components. * Example: uvm_analysis_port #(T)where T is the transaction type. 14. uvm_analysis_imp * Implements the analysis export interface. * Used to connect analysis ports to scoreboards or other analysis components. #uvm #uvmmethodology #fundamentalseries #uvmconcepts #uvmsyntax #verification #testbenches #verificationengineer #training #mirafratechnologies

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Class B amplifiers are sometimes OK for RF but not audio. Why? 👇🏽 Class B amplifiers provide a highly distorted output signal, but with good amplification efficiency. For many RF applications, it is okay to distort the carrier signal as long as the modulation is not affected. The baseband information can still be retrieved. Class B won't work for audio. It is a complex time-varying signal which needs to be accurately amplified. To still get Class B efficiencies, the push-pull amplifier was invented. It is a differential version of a Class B amplifier that can produce amplification with good efficiency. If you'd like to learn more about Class B and push-pull amplifiers, stay tuned for this week's newsletter. ✍🏼 Sign up here: www.viksnewsletter.com What is your experience with Class B or audio? Let me know! ~~ 🔔 Follow me for posts on RF engineering ♻️ Repost if you found it useful.

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the capacitor makes this circuit a low pass filter, as the author suggested the then reduces noise but even if one doesn't necessarily need a low pass filter, it improves phase margin of the feedback configuration (or is high pass in feedback) - very useful for marginally stable designs

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𝑾𝒉𝒚 𝑺𝑻𝑴32 𝒆𝒗𝒂𝒍𝒖𝒂𝒕𝒊𝒐𝒏 𝒃𝒐𝒂𝒓𝒅 ?  I have a range of evaluation boards from all well known semiconductor companies including NxP , ST, Nuvoton, TI , Microchip, Broadcom, Nordic, NVIDIA etc. That was part of my investment. I got loaner boards from ST, NxP and Nuvoton. I used following parameters to decide evaluation board : 1: 𝘾𝙤𝙢𝙥𝙖𝙣𝙮 𝙝𝙞𝙨𝙩𝙤𝙧𝙮 I have used ST devices around 1998 as well. 2: 𝙍𝙤𝙖𝙙𝙢𝙖𝙥 : They have a range of products in various domains 3: 𝘾𝙤𝙨𝙩: It is most important factor and their boards are available in Arduino range as well. 4: 𝙀𝙘𝙤𝙨𝙮𝙨𝙩𝙚𝙢 : They have a variety of tools for Pin multiplexing, Flash programming, Debugging and even for AI. 5: 𝙎𝙪𝙥𝙥𝙤𝙧𝙩 :  I never had issue in contacting ST Marketing , Development , FAE and distributor FAEs . In fact , now my student is also supporting ST devices in India. I was invited for a combined session with faculty as well. 6: 𝙅𝙤𝙗 𝙤𝙥𝙥𝙤𝙧𝙩𝙪𝙣𝙞𝙩𝙞𝙚𝙨 : Since STM32 is based on ARM and being widely used in India. It increases your possibility to get job. Here is outcome of my experience with ST device. This week was little bit interesting in embedded system live sessions. 1: Enabled one US based student in the STM32 evaluation board which I never used. It was done in live session. We supported multiple devices in past but it was instant support over live session. 2: Yesterday also another US based student shared board over camera. We started with default HAL project to do sanity check. First surprise was warning " Obsolete board" . We ignored and continued . Next surprise was "Insufficient flash memory" even with default configuration. This was because it had enabled all peripherals. I asked student to put while(1); in the beginning. Linker was kind enough to discard all other code and we could reach at main() at least. This was simple but important for student to move ahead. Both above students are working professionals in US and joined Embedkari for a refresh cycle. For joining Embedkari, no shubh muhurt is required because every moment is part of God's creation 😀 ... Join anytime . and #salarybadhao #microcontroller #microcontrollers #embedded #embeddedsystem #embeddedlinux #embeddedc #freertos #firmware #firmwareengineer #firmwarejobs #devicedriver #softwareengineers #electronics #embeddedjobs #embeddedsystems #embeddedengineer #embedkari #opentowork #freshers #stm32

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Hi Everyone Today we will discuss about Crosstalk Crosstalk: It occurs when there are parallel running nets of same metal layer for long distance. When a signal on a net switches very fast then, the wires in its surroundings tends to switch too and their logical values or transition can be affected. This is called cross talk. It causes noise bumps in non-switching nets and advancing/delaying of transition in switching nets. They are 2 different types of crosstalk 1)Crosstalk Noise: -->It is undesired change in the logical values of victim due to switching in the input of aggressor. -->If one net is switching and other is at a constant value, the switching net may cause voltage spikes on other net.This is called as cross talk noise. -->Cross talk noise is evolving as a key source in degrading performance and reliability of high speed integrated circuits. 2)Crosstalk Delay: When there is some delay or advancement in output transition of victim due to input transition of aggressor, it is called as cross talk delay. It occurs when some transition is happening in both the nets.Cross talk delay depends on the switching direction of the aggressor and victim nets. # If input transitions in aggressor and victim occur in same direction then output transition of victim becomes faster and it is earlier. It may cause hold violations. ## If input transitions occur in opposite directions then output transition of victim becomes slower and it is delayed, which may cause setup violations. • Ways to fix Crosstalk effects -->Assign Non default routing (NDR) rules by Increasing the spacing. -->Insert buffer to split the long nets -->Jump to different metal layers -->Shielding - Ground lines run in between the signal lines so that they form coupling capacitance with ground. -->By up-sizing the driver of victim net or downsizing driver of aggressor net. Thank you Everyone #Happy learning #Physical Design #VLSI #Semiconductor.

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🚨 **Addressing UPF Supply Undriven Violations in IC Designs Using Synopsys VSLP Tool** 🚨 In Integrated Circuit (IC) design, maintaining robust power management is critical. A key aspect is ensuring that all power supply nets defined in the Unified Power Format (UPF) are properly driven. The Synopsys VSLP tool is essential for identifying and resolving UPF supply undriven violations. Here’s a concise overview of what this entails and its importance. ### **What is UPF Supply Undriven?** **UPF Supply Undriven** refers to instances where supply nets specified in the UPF are not connected to any driving source, leading to potential functional and power management issues. ### **Significance of Resolving UPF Supply Undriven Violations** - **Functional Integrity**: Undriven supply nets can cause parts of the IC to malfunction due to lack of proper voltage, leading to errors. - **Power Efficiency**: Ensuring all supply nets are driven helps optimize power distribution, reducing power wastage. - **Reliability**: Properly driven supply nets minimize the risk of voltage drops and instability, enhancing the IC’s reliability. - **Compliance**: Ensuring all UPF-defined nets are driven is essential for meeting industry standards and ensuring design robustness. ### **Detecting and Resolving UPF Supply Undriven Violations with Synopsys VSLP** The Synopsys VSLP tool provides comprehensive capabilities to detect and address UPF supply undriven violations, ensuring robust and reliable IC designs. #### **1. Static Analysis** - **Supply Net Checks**: The tool scans the design to identify undriven supply nets defined in the UPF. - **Connectivity Verification**: Ensures all power supply nets are properly connected to driving sources. #### **2. Dynamic Verification** - **Power Scenario Simulation**: Simulate different operating conditions to confirm all supply nets are driven as required. - **Dynamic Power Analysis**: Analyze power distribution to identify and rectify undriven supply nets. #### **3. Rule Checking and Reporting** - **Design Rule Checks (DRC)**: Automatically enforce rules related to power supply connections, flagging undriven nets. - **Detailed Reporting**: Generate comprehensive reports outlining undriven supply nets and providing recommendations for correction. ### **Best Practices for Ensuring Driven UPF Supply Nets** 1. **Clear Power Specifications**: Define and adhere to clear power supply specifications for all UPF nets. 2. **Continuous Verification**: Regularly verify supply net connectivity throughout the design process to catch issues early. 3. **Collaborative Approach**: Work closely with design and verification teams to ensure all power nets are properly driven. 4. **Advanced Tool Utilization**: Utilize tools like Synopsys VSLP for automated detection and correction of undriven supply nets. #semiconductors #workwithuppula Thank, Vishnu

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📢 U.S. firm Allegro MicroSystems opens R&D centre in #Hyderabad, to #hire 400 🔥 💡 🔹️Nearly 100 highly skilled professionals have been onboarded and there are plans to scale the headcount to 500 in near future 🔹️ ▪️ #Magnetic #sensing and #power #IC solutions provider Allegro MicroSystems of the U.S. has opened a research and development centre in Hyderabad. ▪️ Nearly 100 highly #skilled #professionals have been #onboarded and there are plans to scale the #headcount to 500 in near future. The facility will be instrumental in #developing #cutting-#edge solutions for e-mobility, clean energy and automation. Setting up of the centre underscores Allegro MicroSystems commitment to advancing #India’s #semiconductor vision and highlights #Telangana’s strategic role in building a resilient, world-class semiconductor ecosystem, Industries and IT Minister D.Sridhar Babu’s office said on the R&D centre opening and the company’s senior leadership meeting him at the Secretariat on Friday (November 15, 2024). ▪️ The R&D facility will be a centre of excellence in #analog and #mixed-#signal #design, #verification and #validation for the #EV, #automotive and #robotic automation markets, driving advanced technological development and positioning Hyderabad as a leader in emerging technology solutions. Allegro MicroSystems’s decision to expand operations in Hyderabad aligns with the city’s robust infrastructure, skilled talent pool and supportive government initiatives. The company’s plans to grow headcount in Hyderabad will create significant job opportunities for skilled professionals, it said. ▪️ The setting up of the centre is a “significant step forward in our global product innovation strategy. Hyderabad’s exceptional talent pool, supportive government policies and strategic location make it an ideal hub for Allegro MicroSystems’s expansion,” CEO Vineet Nargolwala said. ▪️ India is on the verge of a semiconductor revolution and the shift towards electric vehicles is set to drive semiconductor demand since #EVs require significantly more chips than traditional vehicles. India, however, imports over 90% of its semiconductors, the Minister said. Electronics Sector Skills Council Of India (ESSCI) | I) | Electronics India For You | India Electronics and Semiconductor Association | FICCI | India Semiconductor Mission | Semiconductor Nation - Campus Connect | Semicon India | SEMI India | Semiconductor and Electronics | StatsMarketResearch | IETE IETE IETE BIT Mesra, R | hi | IETE | November 15, 2024 | #HYDERABAD | The Hindu Bureau | #AllegroMicroSystems | #chip | #US | #semiconductor | #fabrication | #Jobs | #Business | #market | #technology | #RnD | #RandD | #Semiconductors | #Wafer | thehindu.com #Details— https://lnkd.in/g25E-ia5

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To start verifying the chip in VLSI is a critical task because before that there are series of steps and methodical approach that needs to be followed like verification planning, Test plan creation, Feature extraction, Assertion plan, etc. Below are the brief list of some of the tasks in a systematic manner which are useful for ASIC Verification. [1] To understand the Design Specification and its functionality, involved in Feature Extraction, identify the Test Scenarios, I/O Port List. [2] Identify the different constraints related to clock, timing, delay and power and also define the scope of verification with all the metrics. [3] Ensure the DV guidelines like documentation, regression suite maintenance, bug tracking, coding guidelines, review with designers, etc are followed by everyone. [4] Prepare the Verification Plan which will involve all the metrics of the Verification like the Testbench Architecture, UVC Description, Reference Model, Checkers and the Verification Flow. [5] Prepare the TestPlan, identify the Directed and Corner case scenario. The Plan can be subdivided into Functional Test Cases, Connectivity Checks, Data and Control Path Checks, Register Testing, etc. [6] Start Coding the UVC's and when a basic Testbench Infrastructure is ready, verify it with a Sanity TestCase. [7] Code the Scoreboard and there are multiple ways to do it either with tlm analysis fifo, set of queues and arrays, imp macros, etc. Depending on the need there might be a requirement to design an inorder or out of order comparator and it will check the integrity of TB. [8] Use the Configuration wisely and start with coding more Test Scenario extending from Base Test or a library of Sequences. [9] Prepare a Bug Rate Chart and usually at the initial level Bugs can be caught with the Directed Testcase. But once the Bugs start dropping it's the time to introduce Corner Cases, Functional Coverage and Assertions. [10] Start Preparing a Assertion plan and initiate Functional and Code Coverage. Code Coverage will let you know how much Code has been exercised and Functional Coverage will deal with the Functionality. [11] Launch the Assertion and monitor the report. [12] Launch Formal Verification such as RTL2RTL checks, model checking, LEC, CDC analysis to catch more issues within the design. [13] Identify the coverage Holes and write more Testcases to cover the loopholes. Implement Checkers which are inbuilt in Assertions and it will help more in Verification. [14] When the Coverage goal achieved, launch the GLS (Gate Level Simulation) which is generated over the netlist. [15] To check the Power Aware Verification enabling the UPF based flow. [16] Maintain the regression test suite and keeps running the test for multiple iteration to reduce the probability of occurance of any bugs to zero. The above steps might vary while doing IP, SOC or a subsystem verification. #vlsi #asic #electronics #engineering

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Advanced High-performance Bus (AHB) is a part of AMBA bus which is used as a communication and Interface protocol in Subsystem / IP / SOC based design and is essential for both RTL and ASIC Verification in VLSI. Below are the important concepts that are needed to learn AHB protocol. [1] Role of Arbiter and Decoder in AMBA AHB. [2] Different arbitration mechanism in AHB. (Ex: Round Robin, Priority access, etc) [3] Multi Master - Slave interconnection scheme in AHB. [4] Difference between Incrementing and Wrapping Burst. [5] What is an address and data phase in AHB. Why data phase can accomodate multiple cycle. Waveform for Basic transfer operation. [6] Total maximum No. Of wait states can be inserted as a delay in AHB cycles. [7] Difference between Sequential and Non-seqiential transfer. Role of Idle cycle. [8] What is the role of default Slave and when it is needed. [9] How the address decoding operation execute in AHB. [10] Early Burst termination mechanism. [11] What are the different response mechanism scheme in AHB. Role of HreadyIn and HreadyOut signal. [12] What is the difference between Split and Retry operation. Why OK response execute in single cycle and Error, Retry and Split need at least two cycles. [13] How the arbiter decide which Master to grant access to the bus. Role of HGRANTx and HBUSREQx signal. [14] Role of default master and why it only execute Idle cycle. [15] Locked transfer operation in AHB. [16] How to prevent deadlock when multiple master try to access the bus. How AHB handles multiple split transfer. [17] Operation of AHB bridge in AHB to APB interface. [18] Limit of boundary access in AHB. What will happen if the slave try to access out of bound address range. [19] No. of channels in AHB and it's pipelined architecture. [20] What is the role of dummy master in AHB. #vlsi #asic #semiconductorindustry #electricalengineering

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Overview of Global and Detailed Routing in VLSI Design Follow VLSI Geeks page https://lnkd.in/gQgYpzpc for more..

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