Harsha Vardhan Vudumula

Just a thought RTL Design has few logics which is not required as per the design specifications, this portion of code gets excluded in code coverage analysis. By knowing this fact we still synthesis the logic and it increases the gate counts. but functionaly this logic has no use. Now can this be a area for AI based tool to discard that portion of logic during synthesis and we reduce the gate count?

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Advanced High-performance Bus (AHB) is a part of AMBA bus which is used as a communication and Interface protocol in Subsystem / IP / SOC based design and is essential for both RTL and ASIC Verification in VLSI. Below are the important concepts that are needed to learn AHB protocol. [1] Role of Arbiter and Decoder in AMBA AHB. [2] Different arbitration mechanism in AHB. (Ex: Round Robin, Priority access, etc) [3] Multi Master - Slave interconnection scheme in AHB. [4] Difference between Incrementing and Wrapping Burst. [5] What is an address and data phase in AHB. Why data phase can accomodate multiple cycle. Waveform for Basic transfer operation. [6] Total maximum No. Of wait states can be inserted as a delay in AHB cycles. [7] Difference between Sequential and Non-seqiential transfer. Role of Idle cycle. [8] What is the role of default Slave and when it is needed. [9] How the address decoding operation execute in AHB. [10] Early Burst termination mechanism. [11] What are the different response mechanism scheme in AHB. Role of HreadyIn and HreadyOut signal. [12] What is the difference between Split and Retry operation. Why OK response execute in single cycle and Error, Retry and Split need at least two cycles. [13] How the arbiter decide which Master to grant access to the bus. Role of HGRANTx and HBUSREQx signal. [14] Role of default master and why it only execute Idle cycle. [15] Locked transfer operation in AHB. [16] How to prevent deadlock when multiple master try to access the bus. How AHB handles multiple split transfer. [17] Operation of AHB bridge in AHB to APB interface. [18] Limit of boundary access in AHB. What will happen if the slave try to access out of bound address range. [19] No. of channels in AHB and it's pipelined architecture. [20] What is the role of dummy master in AHB. #vlsi #asic #semiconductorindustry #electricalengineering

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AXI is a multi channel bus which is popularly used as an interfacing protocol between multiple IP's and is useful both in RTL design and ASIC Verification. Below are the key concepts which are needed to understand AXI protocol in depth. [1] Difference between AXI and AHB. Number of Channels used in AXI. Why there is no separate Read response on AXI. [2] What are out of order and outstanding transaction in AXI. [3] What is the address boundary that slave can access in AXI. [4] Transfer mechanism for Write / Read with / without delay. [5] Valid and Ready hand shaking mechanism. What is deadlock condition. How to overcome it. [6] Difference b/w Incrementing and Wrapping Burst. What is a Fixed Burst type. [7] Difference b/w Bufferable and Cacheable type of transaction in AXI. [8] Complete understanding of Exclusive access phenomenon. Difference b/w OKAY and EXOKAY response. [9] What is a Locked access in AXI3. Why it is removed in AXI4. [10] What are the conditions for SLVERR and DECERR. [11] What is a QOS support for AXI4. What are the significance of AxREGION and AxUSER in AXI4. [12] Difference b/w AXI3 and AXI4. [13] What is a write interleaving method in AXI3 and why it's removed in AXI4. #vlsi #asic #semiconductorindustry #electricalengineering

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When I get a chance to talk to freshers (mostly happened in previous company), usually I ask why you want to join the VLSI industry? The responses i used to get are below: 1. I don't know coding, and i dont want to go to the software industry 2. My cousin is working and he/she told me to join 3. My college professor told me that the future of VLSI is bright. 4. I have an interest in digital electronics in Btech and wanted to join a related field. 5. Because my friends are joining so i am joining. Which reason is good? I think there should be interest in doing the job. Because every job is demanding. If there are task which is not of interest, it will feel a burden and create pressure. This will hamper productivity as well as health. Pursuing the field of interest is critical now. what's your thoughts? #job #vlsi #interest #freshersjobs #freshers

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UVM SEQUENCER UVM Sequencer acts as a mediator between Sequence & Driver. It sends the transaction to the driver. The driver then converts this transaction into the pin wiggles to drive the DUT. Let's deep dive into this interesting component - Sequencer. What we will learn? - Purpose of Sequencer - Sequencer class hierarchy - Sequencer methods - Flow of transaction from sequence to driver - Steps to code a sequencer - Sequencer code - Sequencer handles: m_sequencer, p_sequencer Here is the diagram I created to represent the class hierarchy of UVM Sequencer Detailed Video on UVM Sequencer - Link in COMMENT #rtldesign #rtl #digital #digitalelectronics #digitalelectronics #lectures #computerengineering #computerarchitecture #vlsidesign #vlsi #vlsitraining #vlsijobs #vlsiprojects #verification #verificationengineer #physicaldesign #pd #physicaldesignengineer #semiconductor #semiconductorindustry #tcl #scipting #puzzles #problemsolving #career #careerdevelopment #careerguidance #resume #resumebuilding #resumereview #mentor #mentorship #vlsihelpinghands #switispeaks #switipinjani #coding #codinglife #codingtutorial #codingtips #codingjourney #programming #programmer #education #computer #guidance #interview #selfimprovement #selfdevelopment #motivation #careerdevelopment #careers #learning #sv #uvm #systemverilog #soc #ip #asics #cpu #processor #hardwaredescriptionlanguage #cpu #gpu #graphics #supercomputer #tutorial #memories #memory #register #ram #rom #cache

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Choosing the best country to settle as an Indian VLSI (Very-Large-Scale Integration) design engineer depends on factors like job market demand, work-life balance, visa policies, cost of living, and long-term career growth. Here's an analysis of the countries you listed: Countries with Strong Semiconductor/VLSI Prospects 1. Spain and Portugal Why? Semiconductor Expansion: Both countries are benefiting from the EU's focus on strengthening the semiconductor supply chain. Work-Life Balance: Exceptional quality of life with moderate working hours. Challenges: Limited English-speaking roles; knowledge of Spanish/Portuguese may be required. 2. Poland and Romania Why? Emerging Tech Hubs: Growth in tech outsourcing, semiconductor R&D, and embedded systems. Cost-Effective: Lower living costs compared to Western Europe. Challenges: Lower salary scales compared to Western European countries. 3. Italy and Greece Why? Academic-Industry Ties: Good opportunities for research-oriented engineers. Lifestyle Appeal: Excellent for work-life balance. Challenges: Limited industrial semiconductor focus; may suit niche roles. 4. UAE Why? Tech Innovation Push: The UAE is investing heavily in technology and AI sectors. Tax-Free Income: High salaries and tax-free earnings are appealing. Challenges: Fewer semiconductor-specific roles; high cost of living. Countries with Growing Potential 5. Thailand and Malaysia Why? Established Manufacturing Base: Both countries are integral to the global semiconductor supply chain. Low Cost of Living: Affordable for Indian engineers. Challenges: Manufacturing-focused roles may dominate over design or R&D. 6. Mexico Why? Proximity to the U.S. Market: Growing demand for skilled engineers due to the North American semiconductor boom. Affordable Lifestyle: Low cost of living. Challenges: Limited advanced design roles; mostly production-oriented jobs. 7. Uruguay Why? Quality of Life: Known for safety and high living standards in Latin America. Challenges: Limited semiconductor industry; more focused on IT and software. Niche Markets with Limited Scope 8. El Salvador, Panama, Costa Rica, Serbia, and Montenegro Why? Smaller Economies: Less focus on high-tech industries. Opportunities: IT outsourcing rather than VLSI design. Challenges: Limited career growth in semiconductor design. Key Recommendations 1. For Immediate Career Growth: Spain, Portugal, Poland, Romania, UAE are the best for VLSI engineers looking for design/R&D roles and a blend of lifestyle and career opportunities. 2. For Manufacturing and Support Roles: Malaysia, Thailand, and Mexico offer better opportunities for production-related roles with future scope in advanced semiconductor processes. 3. For Research and Academic Growth: Italy and Greece may be suitable for research-oriented engineers. 4. Long-Term Viability: Spain, Portugal, UAE, and Poland stand out for future scope, government investment in tech, and global connectivity.

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To start verifying the chip in VLSI is a critical task because before that there are series of steps and methodical approach that needs to be followed like verification planning, Test plan creation, Feature extraction, Assertion plan, etc. Below are the brief list of some of the tasks in a systematic manner which are useful for ASIC Verification. [1] To understand the Design Specification and its functionality, involved in Feature Extraction, identify the Test Scenarios, I/O Port List. [2] Identify the different constraints related to clock, timing, delay and power and also define the scope of verification with all the metrics. [3] Ensure the DV guidelines like documentation, regression suite maintenance, bug tracking, coding guidelines, review with designers, etc are followed by everyone. [4] Prepare the Verification Plan which will involve all the metrics of the Verification like the Testbench Architecture, UVC Description, Reference Model, Checkers and the Verification Flow. [5] Prepare the TestPlan, identify the Directed and Corner case scenario. The Plan can be subdivided into Functional Test Cases, Connectivity Checks, Data and Control Path Checks, Register Testing, etc. [6] Start Coding the UVC's and when a basic Testbench Infrastructure is ready, verify it with a Sanity TestCase. [7] Code the Scoreboard and there are multiple ways to do it either with tlm analysis fifo, set of queues and arrays, imp macros, etc. Depending on the need there might be a requirement to design an inorder or out of order comparator and it will check the integrity of TB. [8] Use the Configuration wisely and start with coding more Test Scenario extending from Base Test or a library of Sequences. [9] Prepare a Bug Rate Chart and usually at the initial level Bugs can be caught with the Directed Testcase. But once the Bugs start dropping it's the time to introduce Corner Cases, Functional Coverage and Assertions. [10] Start Preparing a Assertion plan and initiate Functional and Code Coverage. Code Coverage will let you know how much Code has been exercised and Functional Coverage will deal with the Functionality. [11] Launch the Assertion and monitor the report. [12] Launch Formal Verification such as RTL2RTL checks, model checking, LEC, CDC analysis to catch more issues within the design. [13] Identify the coverage Holes and write more Testcases to cover the loopholes. Implement Checkers which are inbuilt in Assertions and it will help more in Verification. [14] When the Coverage goal achieved, launch the GLS (Gate Level Simulation) which is generated over the netlist. [15] To check the Power Aware Verification enabling the UPF based flow. [16] Maintain the regression test suite and keeps running the test for multiple iteration to reduce the probability of occurance of any bugs to zero. The above steps might vary while doing IP, SOC or a subsystem verification. #vlsi #asic #electronics #engineering

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VLSI Career FAQ's A lot of common questions from VLSI Aspirants were answered in a podcast. Here's the list: 1. Career opportunities 2. Professional networking 3. Free online resources 4. Practice platforms 5. Resume building 6. Making your resume stand-out 7. How to be in top 1% applicants 8. Right way to connect through professionals 9. Get referrals 10. Overcome nervousness 11. Skillsets to focus on 12. Off campus placement 13. Gate preparation 14. How to get in industry with tier-3 college & a lot more.... If you are looking for answers to any of above queries, go through the detailed video which will resolve your queries. Sharing the Link in COMMENT NOTE: We will have many more such Live sessions. I will post details about next Live session soon where I will join you Live & resolve your queries. #rtldesign #rtl #digital #digitalelectronics #digitalelectronics #lectures #computerengineering #computerarchitecture #vlsidesign #vlsi #vlsitraining #vlsijobs #vlsiprojects #verification #verificationengineer #physicaldesign #pd #physicaldesignengineer #semiconductor #semiconductorindustry #career #careerdevelopment #careerguidance #resume #resumebuilding #resumereview #mentor #mentorship #vlsihelpinghands #switispeaks #switipinjani #coding #codinglife #codingtutorial #codingtips #codingjourney #programming #programmer #education #computer #guidance #interview #selfimprovement #selfdevelopment #motivation #careerdevelopment #careers #learning #sv #uvm #systemverilog #soc #ip #asics #cpu #processor #hardwaredescriptionlanguage #cpu #gpu #graphics #supercomputer #tutorial

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While Verilog is used as coding for RTL design but due to the rich feature set and simplicity, Systemverilog (SV) is now widely used as a preferable HDL language. Below are the reason why adopting SystemVerilog is essential for writing efficient RTL code in comparison to Verilog. [1] FSM implementation in SystemVerilog(SV) is easier using enum data type instead of using parameter in Verilog. Enum has number of methods like first, last, next, previous which are useful in debugging and running through the code. Moreover enum will take care of legal and illegal assignment unlike parameter which is also hard-coded. Using Enum the length of the code can also be reduced. [2] The single always block in verilog is replaced with three separate always block in SV like always_comb for combinational logic, always_ff for sequential logic and always_latch for inferring latch which makes the RTL code more readable and implementing separate logic. [3] Documenting code in SV is much easier as compared to Verilog due to repeated named labelling at the beginning and end of the block. [4] case inside operator of SV replaces the casex and casez statements in verilog. [5] SV introduces interface construct which helps in bunching the signals interacting with DUT and therefore reducing the complexity of the port connection and instantiation within Verilog. Interface also helps in code reduction by bunching different subroutine calls and methods. [6] SV uses structure in the form of struct construct which are useful in grouping of different data items or signals of different data type under one label which significantly reduces code length and removes the problem of assignment mismatch. [7] SV introduces unique and priority statements which removes the problem of overlapping case condition and non matching of any case statements in parallel and full case statements of verilog. [8] SV supports do while loop for execution while Verilog doesn't support it. [9] SV introduces wildcard, break, continue, increment and decrement operator which makes an RTL code more efficient and less lengthy. [10] SV introduces Logic keyword which is driven by procedural block and continuous assignment statements and can be used in place of reg and wire in verilog and the language will decide based on the need. [11] SV introduces foreach loop apart from the other looping construct of verilog which helps to iterate through arrays. [12] SV has support for assertions and has support for keywords like assert and assume which are useful for Hardware acceleration boxes in FPGA while Verilog has very limited support for assertions. [13] SV provides void function which are synthesizable and these function do not required to have a return type and can be used in place of subroutine calls and methods like tasks to make the RTL code synthesizable. #vlsi #asic #electronics #engineering

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8 Promsing Job Profiles for Freshers in VLSI (with Job Description) 🚀 RTL Design Engineer: The workhorse of front-end design, responsible for translating system specifications into functional RTL code using Verilog or VHDL. They ensure code readability, maintainability, and adherence to coding standards. Example: Designing the control unit for a processor using RTL. 🚀 Verification Engineer: Guarantees the design's correctness by creating test benches, writing test cases, and running simulations. They collaborate with RTL designers to fix bugs and ensure the design meets functional specifications. Example: Developing a test bench to verify if a multiplier unit produces the correct output for various input combinations. 🚀 Design-for-Test (DFT) Engineer: Integrates test circuitry into the design to enable efficient post-manufacturing testing. They understand various DFT techniques and ensure minimal area and performance overhead. Example: Implementing scan chains to facilitate easier testing of internal logic blocks. 🚀 Physical Design Engineer (In some cases for freshers): While typically a back-end role, some companies might offer opportunities for freshers to assist with initial floorplanning tasks or placement of standard cells. Example: Assisting with floorplanning the top-level blocks of a design to optimize chip area. 🚀 FPGA Design/Prototyping Engineer: Utilizes FPGAs (Field-Programmable Gate Arrays) to emulate the design behavior before chip fabrication. They perform RTL-to-FPGA synthesis and leverage debugging skills to identify and fix issues. Example: Implementing a communication protocol on an FPGA to validate its functionality before integrating it into the final chip design. 🚀 Logic Synthesis Engineer: Focuses on optimizing the RTL code for efficient synthesis into a gate-level netlist. They understand synthesis tools and techniques to ensure the design meets performance and area constraints. Example: Analyzing the critical path of a design and applying optimizations to improve its timing performance during synthesis. 🚀 Low-Power Design Engineer: Emphasizes techniques to reduce power consumption in the design. They explore clock gating, power gating, and voltage scaling methods while ensuring functional correctness. Example: Implementing clock gating for unused portions of the design to minimize dynamic power consumption. 🚀 Pre-Silicon Validation Engineer: Concentrates on validating the design functionality in a simulated environment before silicon fabrication. They utilize simulation tools, scripting languages, and verification methodologies to ensure a robust design. Example: Developing a comprehensive verification plan to cover various corner cases and stress scenarios using simulation tools. A detailed post is in comments. For all semiconductor and AI related content, follow TechoVedas

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I come across multiple folks every year who want to switch job profile. It becomes difficult to switch after 2 years if person is not ready to relocate and compromise with salary. This is one of the reasons I recommend students to try embedded software career path first. I have conducted several surveys in LinkedIn for awareness purpose. Learning firmware or embedded software will definitely add value to PCB design background folks. Experienced folks can explore management role after firmware development skills. We have many hardware background folks in our Developer kit community. They got better opportunities after learning firmware programming. Our Ultra kit (Six months live session) can definitely help such folks due to several features: a: Learn C in various levels starting from Level 1. It depends on various types of C used in embedded software development. It includes logic building and project based hands-on approach. We have enough testimonials of C skills improvement in both students and working professionals. b: With longer duration, we can provide learning material for various architectures, RTOS, Linux and testing as well. c: PCB design background folks can try to design complete product. We have provision for this as well based on my past experience. Answer : This is possible but the complete switch over to embedded software will take some time. There are several factors : 1: If you are from an ECE background, you might have studied Microprocessor and Digital Electronics. If not, you have to study these two first. 2: You have to work on your C skills and learn firmware development with ARM based MCU. 3: If your current CTC is above 14 LPA , you have to first try to find firmware development in your organization. 4: You may also explore the team lead kind of role where you get some opportunity to work in firmware development.. 5: RTOS and Linux Application development can add value to your profile. 6: You have to be flexible for relocation. 7: Learning firmware development will definitely add value to your profile even if you don't get an immediate opportunity to switch. Answer to I have been working as PCB's design engineer for the past 7 years. I would like to switch over to the embedded software field. Is it possible? by Sanjay Kumar https://lnkd.in/gWtyirVq #embedded #opentowork #pcbdesign #embedkari

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Mostly asked Interview question: What is Blocking and Non-blocking Assignments in Verilog? 🤔 Whether you're a seasoned engineer or just starting out, understanding these concepts is crucial for writing efficient and bug-free code. In this video, you will learn: --> The fundamental differences between blocking (=) and non-blocking (<=) assignments. --> When and why to use each type of assignment. --> Common pitfalls and best practices. --> Practical examples to illustrate these concepts in action. Understanding the proper use of blocking and non-blocking assignments can significantly improve your design verification process and help you avoid common issues. 🔗 Check out the video here: https://lnkd.in/dEucX_aR I hope you find this video informative and helpful. Don’t forget to like, comment, and subscribe to my channel (VLSI with Jatin) for more insightful content on design verification and Verilog programming. Feel free to share this with your network and let me know your thoughts or any questions you might have in the comments below! #verilog #designverification #blockingAssignments #nonblockingassignments #vlsi #engineering #semiconductor #hardware #skills #freshgraduates #vlsiengineering #vlsijobs #vlsijobseekers #careerguidance #mockinterviews #interviewprep #ushiring #usajobs #opentowork #h1b #semiconductorjobs #designverification #verificationengineer #systemverilog #uvm #siliconvalley #opentowork #activelylooking #uscitizens #freshersjob #vlsiwithjatin

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Hi my people🌷, Keep moving on. Let’s chat something today📝one more interesting topic 📍 Please check ,I mentioned below and read understand,thank you . There are several ways to fix an ASIC-based design. >From easiest to most extreme: RTL Fix -> Gate Fix -> Metal Fix -> FIB Fix First, let's review fundementals. A standard-cell ASIC consists of at least 2 dozen manufactured layers/masks. Lower layers conists of materialsmaking up the actual CMOS transistors and gates of the design. The upper 3-6 layers are metal layers used ti connect everything together. ASICs, of course, are not intended to be flexible like an FPGA, however, important "fixes" can be made during the manufacturing process. The progression of possible fixes in the manufacturing life cycle is as listed above. An RTL fix means you change the Verilog/VHDL code and you resynthesize. This usually implies a new Plance&Route. RTL fixes would also imply new masks, etc. etc. In other words - start from scratch. A Gate Fix means that a select number of gates and their interconections may be added or subtracted from the design (netlist). This avoids resynthesis. Gate fixes preserve the previous synthesis effort and involve manually editing a gate-level netlist - adding gates, removing gates, etc. Gate level fixes affect ALL layers of the chip and all masks. A Metal Fix means that only the upper metal interconnect layers are affected. Connections may be broken or made, but new cells may not be added. A Sewing Kit is a means of adding a new gate into the design while only affecting the metal layers. Sewing Kits are typically added into the initial design either at the RTL level or during synthesis by the customer and are part of the netlist. A Metal Fix affects only the top layers of the wafers and does not affect the "base" layers. Sewing Kits are modules that contain an unused mix of gates, flip-flops or any other cells considered potentially useful for an unforseen metal fix. A Sewing Kit may be specified in RTL by instantiating the literal cells from the vendor library. The cells in the kit are usually connected such that each cell's output is unconnected and the inputs are tied to ground. Clocks and resets may be wired into the larger design's signals, or not. A FIB Fix is only performed on a completed chip. FIB is a somewhat exotic technology where a particle beam is able to make and break connections on a completed die. FIB fixes are done on individual chips and would only be done as a last resort to repair an otherwise defective prototype chip. Masks are not affected since it is the final chip that is intrusively repaired. Clearly, these sorts of fixes are tricky and risky. They are available to the ASIC developer, but must be negotiated and coordinated with the foundry. ASIC designers who have been through enough of these fixes appreciate the value of adding test and fault- tolerant design features into the RTL code so that Software Fixes can correct mior silicon problems.

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One of the important aspect in Verifying a RTL design is to use Assertion Based Verification (ABV) techniques. Assertions are used as a check against a design. For VLSI, someone needs to provide equal emphasis to SystemVerilog Assertions (SVA) in addition to Verilog, SV, Digital Design, etc. Below are some of the advantages of using Assertions in both RTL design and Verification: [1] SVA has to be written by both RTL designers and Verification engineers. RTL assertions mostly deals with microarchitectural specification while verification engineers deals with interface and functionality based assertions. [2] SVA improves the Observability of the design and thereby reducing the overall debug effort. This can be achieved by inserting various check points within the specific areas of the design to check the effect of internal bug instead of waiting for the entire Testcase to complete and then to backtrace the signal to find out the bug. [3] SVA can be written at multiple places within the Testbench like interfaces, monitor, scoreboard and even using bind with the top module to improve the probability of catching bugs within the design. [4] SVA has the keyword called as “cover” which will make sure the assertions are covered and is also used as a key indicator to measure verification progress. [5] SVA reduces the time to bring up the code because a simple logic may became cumbersome while trying to implement with Verilog and hence it makes the code more readable. Property P1; @(posedge clk) abc |-> ##[1:2] cd; endproperty assert property (P1); [6] SVA has assertion directives like assume, expect and restrict apart from assert which can be used in coding several temporal assertion as per the requirement. [7] Assertions has the capability to capture specific scenarios to measure coverage which is a important parameter to close coverage. [8] Since assertions are by default always on, they are useful in tracking the Testcases faster in case of any error. #vlsi #asic #electronics #electricalengineering

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Comprehensive guide for VLSI enthusiasts interested in RTL Design along with links of important papers and spec: [1] Digital Electronics: ✓ Good understanding on Combinational, Sequential circuits, FSM and logic gates. ✓ Questions on Skew, Slew, Setup and Hold Window, Metastability, Hold Slack calculation, Synchronizers. Source to learn: ✓ Digital Design by Morris Mano, Digital Design by JF Wakerly, FSM problems from the Digital design book by Charles Roth. [2] Verilog: ✓ Understanding on concepts like continuous assignment, blocking, nonblocking, data types, task/function, delays, data flow and structural modelling style, UDP, Event Queue execution ✓ Coding related to all Combinational and Sequential ckt, sequence detector coding for overlapping and non overlapping FSM (both Mealy and Moore) Sources: ✓ Verilog book by Samir Palnitkar and J bhaskar. ✓ Practice code from edaplayground or open source simulators. [3] SystemVerilog: ✓ First understand the difference b/w Verilog and SV and why do we need SV. ✓ Synthesizable and non Synthesizable constructs. ✓ Concepts of SV interface, arrays, data type like logic, SV event queues. ✓ Re code the same Combinational, Sequential and FSM with SV constructs. Sources: ✓ SV for Design by Stuart Sutherland ✓ 1800.2-2023 SV LRM (focussing the design constraints) [4] IP / Protocol: ✓ All the AMBA protocols like AHB, APB, ATB, AXI, ACE. ✓ Communication protocol like I2C and SPI ✓ Synchronous and Asynchronous FIFO ** Link in comments** [5] Miscellaneous Topics: ✓ Coding guidelines for RTL (Extremely important) ✓ Good understanding on ASIC and FPGA flow. ✓ CDC concepts ✓ Fast and Slow data path calculation ✓ RDC flow and execution #vlsi #asic #semiconductorindustry #electricalengineering

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From Light Switches to Laptops: How logic Gates Define the World of Digital VLSI Design? 🚀 Imagine tiny switches that can be turned on or off with electricity. These are basically logic gates, the building blocks of digital circuits. They take electrical signals as inputs (like a light switch being flipped on or off), perform a simple logical operation on those signals, and then output a new signal based on that operation. 🚀 Logic gates perform basic operations like AND, OR, and NOT: AND Gate: The output is on (1) ONLY if ALL inputs are on (1). OR Gate: The output is on (1) if ANY input is on (1). NOT Gate: The output is the inverse of the input, flipping the signal (if the input is 1, the output is 0, and vice versa). By combining these simple operations in different ways, you can create complex digital circuits for all sorts of functions in a computer or device. 🚀 Light switch: Imagine a simple light controlled by two switches. You want the light to be on only if BOTH switches are flipped on (think of a hallway light needing two switches at either end). This can be achieved with an AND gate. One input comes from each switch, and the output from the AND gate goes to the light bulb. Only when both inputs (switches) are on (flipped) will the output (light) turn on. 🚀 Security system: Let's say you have a security system with a motion sensor and a door sensor. You want an alarm to sound if EITHER the motion sensor detects movement OR the door is opened. This can be built with an OR gate. One input comes from the motion sensor and the other from the door sensor. If EITHER input (sensor) detects something (goes on), the output from the OR gate will trigger the alarm. 🚀 Traffic light controller: This one requires a combination of gates. We can use an AND gate to ensure both the pedestrian button is pressed AND there are no cars detected to allow pedestrian crossing. Similarly, we can use an OR gate to ensure EITHER a timer runs out OR a car is detected to switch the light to green for traffic. 🚀 Basic arithmetic: Logic gates can even be used for simple math. By combining AND, OR, and NOT gates in specific ways, you can create circuits that perform operations like addition or subtraction on binary numbers (0s and 1s). These are the building blocks for more complex arithmetic units in computers. A detailed post is in comments. For all semiconductor and AI related content, follow TechoVedas

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Basic and Simple Blueprint to structure a project in UVM [Important for VLSI Professionals] UVM is a preferred verification language due to its reusability, scalability, interoperability, CRV, proper phasing, etc. Below are the most simplest basic steps mentioned as how to develop a TB infrastructure from scratch. Step 1: Documentation ✓ Go through the specification thoroughly and prepare the Verification Plan, Test Plan, Assertion Plan and understand the working of the IP or protocol. Step 2: Coding ✓ Code the interface by listing all the I/O port. Code the Clocking block to avoid race condition, synchronization and direction to TB. Optionally code the Modport. *** Note: Cautiously use the input / output skew and the clockvar There are certain rules while using the Clocking block and modport which someone needs to follow. **** ✓ Code the transaction class and use the randomization wherever applicable. Try to avoid the field macros and instead use proper methods. **General thumb rule the input should be rand. Moreover try to use the do_copy, do_ compare, convert2string, do_print methods instead of using field macros which has a overhead** ✓ Code the driver logic for the pin level activity at DUT. Use sequencer driver handshake properly depending on pipelined / non pipelined access. *** Use proper coding guidelines while coding driver logic *** ✓ Code the Sequencer and use arbitration mechanism if needed. ✓ Code the Monitor to handle the transaction. The analysis port first needs to be connected to Agent and then to other subscribers like scoreboards, etc. ✓ Build the agent and give proper instantiation for Driver, monitor, and Sequencer. Depending on application the Agent can be chosen as either active or passive. ✓ Code the env class and give proper connection. ✓ Write some basic sequence items to check the flow along with base test class. While coding the sequence items number of methods can be used to execute the sequence. ** While using the sequence use start_item/finish_item instead of `uvm_do macro ** ✓ Code the scoreboard either with the help of tlm fifo, associative array, queue depending on whether it's used in order or out of order comparator. The coding style will change depending on need. ** While designing the Scoreboard make sure the predictor and evaluator are separate** There are almost 6 to 7 different methods of designing a scoreboard ✓ Code the top module and use of run_test and set the config db. *** Above are some of the very basic steps mentioned but ideally the testbench will be complex and use many more concepts which are not mentioned above. Some of them are: ✓ Virtual Sequencer and Virtual Sequences. ✓ RAL ✓ Callbacks ✓ Objection mechanism ✓ Config and resource db ✓ Coverage ✓ Assertions #vlsi #asic #electronics #electricalengineering

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🚀 Analog VLSI: The Silent Powerhouse Driving Quantum Computing 🧑‍💻 In the rapidly evolving landscape of Quantum Computing 🌐, where qubits, entanglement, and superposition are the buzzwords, there's an unsung hero that's playing a pivotal role—Analog VLSI. Let's delve into how Analog VLSI is contributing to this cutting-edge technology and why it's indispensable! 🔍 #1️⃣ The Foundation of Precision Quantum computing relies on the manipulation of quantum states, which demands ultra-precise control over signals. 🎛️ Analog VLSI circuits excel in generating and processing continuous signals with high fidelity, enabling the precise control needed to manipulate qubits effectively. Without this precision, the delicate quantum states could easily be disrupted, leading to computational errors. ⚠️ #2️⃣ Bridging the Classical-Quantum Divide One of the challenges in quantum computing is the interface between classical and quantum domains. Analog VLSI provides a seamless bridge 🌉 by enabling efficient data conversion and signal processing. Through high-speed Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs), it translates quantum information into classical data formats, allowing for effective monitoring, control, and error correction in quantum systems. 🖥️ #3️⃣ Power Efficiency at Its Best In quantum computing, maintaining qubit coherence requires low temperatures, often near absolute zero ❄️. This poses significant challenges in power management. Analog VLSI circuits are inherently power-efficient, ensuring minimal thermal noise and heat generation. This efficiency is crucial in maintaining the delicate balance required for qubits to function properly over extended periods. 🕒 #4️⃣ Real-Time Signal Processing Quantum computers require real-time signal processing to maintain qubit coherence and perform operations swiftly. Analog VLSI, with its fast response times and low-latency signal processing capabilities ⏱️, is key to ensuring that quantum operations are executed with the speed and accuracy required for practical applications. #5️⃣ Scalability and Integration As quantum computing scales up, the integration of numerous qubits and control circuits becomes complex. Analog VLSI offers high-density integration capabilities, allowing for the compact design of quantum processors. This integration is critical in developing scalable quantum systems that can handle more qubits and deliver higher computational power. 📈 #6️⃣ The Future Outlook The fusion of Analog VLSI with quantum computing technology is paving the way for new frontiers in computing power and efficiency. As we advance toward practical quantum computers, the role of Analog VLSI will only grow more prominent, becoming the backbone that supports the next wave of technological breakthroughs 🌍. Follow Soumick Majumdar for more such technical content. Happy Connecting !!! #QuantumComputing #AnalogVLSI #VLSI #iiitb #gate #gate2025 #innovation

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