Naveen Shanwad

Naveen Shanwad

Pune, Maharashtra, India
3K followers 500+ connections

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About

Experienced in full cycle asic verification (dynamic & formal) , architecture and rtl…

Activity

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Experience

  • NVIDIA Graphic

    NVIDIA

    Pune, Maharashtra, India

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    Austin, Texas Metropolitan Area

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    Hillsboro, Oregon, United States

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    Portland, Oregon Area

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    Portland, Oregon Area

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    Portland, Oregon Area

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    San Jose, California

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    Chandler, Arizona, United States

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    Bangalore

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    Bangalore, India

Education

  • Arizona State University Graphic

    Arizona State University

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    Activities and Societies: IEEE-SJCE (Member of Executive Committee) IEEE-Electron Devices Society (Vice Chairman year 2009)

    Member of core planning committee,CYBERIA - 09, an annual technical Fete of IEEE SJCE.
    Part of college football B team.
    Organizer of Decibel 2010 , an annual cultural fest of department of ECE, SJCE .

Licenses & Certifications

Volunteer Experience

  • Habitat for Humanity East Bay Graphic

    Volunteer

    Habitat for Humanity East Bay

    - Present 9 years 6 months

    Social Services

    Build Playhouses for children
    Activities included drawing & painting, cutting the board and fitting the playhouse

  • Brocade Graphic

    Volunteer

    Brocade

    - Present 10 years 8 months

    Children

    Helped to build play house for children of veterans
    Drew colorful paintings on wooden walls of play house

  • Intel Corporation Graphic

    Volunteer - Be Kind project

    Intel Corporation

    - Present 11 years 9 months

    Education

    Helped to prepare Be Kind packets to teachers and students

  • Akamai Technologies Graphic

    Participant, Flash Mob

    Akamai Technologies

    - Present 13 years 3 months

    Disaster and Humanitarian Relief

Courses

  • Advanced Analog Integrated Circuits

    EEE 527

  • Advanced Hardware System Design

    CSE 591

  • Computer Architecture

    CSE 598

  • Digital Signal Processing

    EEE 591

  • Digital Systems and Circuits

    EEE 591

  • Enterprise Modeling

    IEE 530

  • Low Power Bioelectronics

    EEE 598

  • Memory System: Device, Circuit and Architecture

    CEN 591

  • VLSI Design

    ESE 525

Projects

  • Verification of a Packet Router

    Verified a 4 port packet router using system verilog test bench environment
    The DUT consisted of single input port (fast clock domain) and four output ports (slow clock domain)
    Verified basic functionalities, boundary cases and special features of DUT.
    Verified the special flags to stop the incoming traffic whenever required
    Environment consist of generator,driver, bfm, receiver, scoreboard & monitors.
    Added SV assertions and cover groups to enhance testability.

  • Design & Verification of Asynchronous FIFO

    RTL design of async fifo in Verilog.
    Verified design using System Verilog testbench environment
    Created a layered testbench with Bus Functional Modules, Driver, Reciever & Scoreboard


  • 32 bit MIPS Processor Design & Verification in Verilog

    Designed RTL behavioral description for combinational & sequential parts of MIPS CPU
    Tested design at block level & complete system level in Verilog using Active-HDL student edition tool
    Built checker functions, added both directed & random test stimulus to validate the design

  • Cross Point Memory Architecture - Emerging non-volatile memories

    Collaborative study on emerging non volatile memory arrays with respect to device, circuit and architecture level
    Effect of sneak paths and sense amplifier design, read & write margin degradation
    Studied challenges associated with the memory systems below 10nm and suggested solutions for the implementation of crossbar resistive memory.

    Other creators
    • Karthikeya Palepu

  • 128 bit Hamming Code(SECDED) RTL synthesis and Verification

    Wrote behavioral model for 128 bit Single Error Correction & Double Error Detection Hamming code in Verilog.
    Synthesized it using RC Synthesis tool from Cadence (45nm technology library)
    Logic Validation for different error types (single, double)
    Timing and Power analysis.



  • Performace analysis of different Cache Replacement policies

    Evaluated different cache replacement policies on Bzip2,Gcc and Mcf benchmarks from Spec2000 suite.
    Cache miss rates evaluation for Static, Dynamic and Bimodal Re-Reference Interval Prediction policies
    Implemented Dynamic Insertion Policy(DIP) in for above benchmarks and evaluated against Least Recently Used (LRU) policy.

  • Standard Cell Library Design using 45nm technology

    - Present

    Design and layout of basic Logic gates, Combinational & Sequential circuits using 45nm PDK.
    Simulation using HSPICE and SPECTRE.
    Abstract view generation for APR tools.
    Statistical timing analysis and leakage analysis of cells using encounter library characterizer (ELC)

  • Frequency Domain Adaptive Noise Cancellation using MATLAB

    Designed an adaptive filter to cancel noise from corrupted input signal using a reference signal.
    Implemented the algorithm using MATLAB and simulated.
    Calculated performance measures for two different types of input signals.
    SNR measurement for different values of adaptive coefficients to get estimate of convergence vs resolution of output signal.

    Other creators

  • RFID Based Patient Tracking System

    Bachelor Thesis: RFID based patient tracking system using TI’s MSP430 and zigbee module(EZ430 RF2480) was designed and implemented. The project involved a novel approach of tracking the patients’ locations inside a hospital by setting up a Zigbee WPAN. Patients were to be given sensors comprising of a RF2480 ZigBee wireless sensor node interfaced with a TSOP 1738 IR sensor. The IR sensor picks up the encoded location data of the patient and transmits to a remote zigbee server where the location…

    Bachelor Thesis: RFID based patient tracking system using TI’s MSP430 and zigbee module(EZ430 RF2480) was designed and implemented. The project involved a novel approach of tracking the patients’ locations inside a hospital by setting up a Zigbee WPAN. Patients were to be given sensors comprising of a RF2480 ZigBee wireless sensor node interfaced with a TSOP 1738 IR sensor. The IR sensor picks up the encoded location data of the patient and transmits to a remote zigbee server where the location is logged in. The project was sponsored by Philips.

    Other creators

Honors & Awards

  • Best Student 2004

    Rotary Club, Belgaum, India

  • Ranked 1st in state for All India Chintana Mathematics Exam

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Languages

  • Kannada

    Native or bilingual proficiency

  • Hindi

    Native or bilingual proficiency

  • Marathi

    Native or bilingual proficiency

  • English

    Professional working proficiency

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