Arunanshal Gera

© Topic: VLSI Glossary © ⏭ ⏭⏭ ⏭ GrowVLSI ⏮ ⏮ ⏮ ⏮ (A-S posted few days back) T: TB- Tera Byte TN- Technology Node TG- Transmission Gate TTL- Transistor Transistor Logic TT- Typical Typical (TT is the corner where both NMOS and PMOS are typical, when this corner is enabled the processing parameters may be typical/hard because corner analysis does include all the process variation possiblities ) TCL- Tool Command Language TF- Technology File 😍It is an ASCII file in which information about all the metal layers, vias and their design rules are available😍 TLU+: Timing Library Update/Table LookUp 😍 TLU+ file provides RC parasitic information of metal per unit length which is used to calculate the net delay. All TLU+ file data is completely technology dependent and is given by Foundry 😍 TNS- Total Negative Slack U: ULVT- Ultra Low Threshold Voltage UPF- Unified Power Format ULSI- Ultra Large Scale Integration V: VLSI- Very Large Scale Integration VHDL- VHSIC(Very High Speed Integrated Circuit) Hardware Descriptive Language W: WNS- Worst Negative Slack X, Y, Z: Didnot find anything Content Writer B. Lokeshwar

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#SmartSoCSolutions! #Hiring #Belowopenpositions #Bangalorehiring Interested can share their profile to ramya.samanthula@smartsocs.com 1. Lead DV Profiles for BLR location – 7 to 12yrs 2. DFX-DV (DFD/DFT)- (AMD flow) #MBIST - Pattern simulation/ATE/CReST skill as well with 5+ experience-  BLR Location  3. DV -AMD FLOW - 4-20 yrs -BLR ( Exp in Integration , PG /PM ( power ),Security ,CDP ( core data path ) .NBIO ( north bridge input output) , GDP ) ( Graphics data path ( GFX) 4. CPU verification , PCIE ,DDR & HBM ( High Bandwidth Memory ),CXL - 4-10 yrs

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Why we need to choose a VLSI as a career As of my last knowledge, the field of Very Large Scale Integration (VLSI) in India has been experiencing significant growth and offers a promising scope for individuals interested in pursuing a career in this field. Here are some points highlighting the scope of VLSI in India: Job Opportunities: The semiconductor industry in India has been growing steadily, with many multinational companies establishing their presence in the country. This has led to an increase in job opportunities for VLSI engineers in India. Companies like Intel, Qualcomm, AMD, NVIDIA, and many others have research and development centers focusing on VLSI design in India. Research and Development: India has seen a rise in the number of research and development activities in the field of VLSI. Many academic institutions and research organizations are actively involved in cutting-edge research in VLSI design, leading to innovations in the field. Start-up Ecosystem: The VLSI industry in India has seen a growth in the number of start-ups focusing on semiconductor design and related technologies. These start-ups are working on niche areas of VLSI design and are contributing to the overall growth of the industry. Training and Skill Development: There are several training institutes and programs in India that offer courses in VLSI design. These programs help individuals acquire the necessary skills and knowledge required to pursue a career in VLSI. Collaboration with Industry: Many academic institutions in India have collaborations with industry partners to provide students with exposure to real-world projects and opportunities for internships. This collaboration helps in bridging the gap between academia and industry. Government Initiatives: The Indian government has been taking initiatives to promote the growth of the semiconductor industry in the country. Initiatives like the National Policy on Electronics and the Electronics Manufacturing Clusters (EMC) scheme aim to boost the electronics and semiconductor ecosystem in India.

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🚨 **Ensuring Proper PG Bias Off State in IC Designs Using Synopsys VSLP Tool** 🚨 In Integrated Circuit (IC) design, managing power gating bias off states correctly is crucial for optimizing power efficiency and ensuring reliable operation. The Synopsys VSLP tool is essential for detecting and resolving pg_biasoff_state issues. Here’s a concise overview of what pg_biasoff_state entails and its importance. ### **What is PG Bias Off State?** **PG Bias Off State** refers to the condition where biasing of power-gated domains is correctly turned off to save power. Ensuring this state is properly managed is vital for achieving power efficiency and maintaining functional integrity. ### **Importance of Addressing PG Bias Off State Violations** - **Power Efficiency**: Proper management of bias off states reduces power consumption, enhancing the overall energy efficiency of the IC. - **Functional Integrity**: Correctly handling bias off states ensures that power-gated domains are fully powered down without unintended leakage or partial functionality. - **Reliability**: Ensuring proper bias off states enhances the reliability and stability of the IC, preventing potential issues from partial biasing. - **Thermal Management**: Reducing power consumption through effective bias off state management helps in thermal management by lowering heat generation. ### **Detecting and Addressing PG Bias Off State Violations with Synopsys VSLP** The Synopsys VSLP tool provides advanced capabilities to detect and rectify issues related to PG bias off states, ensuring robust and reliable IC designs. #### **1. Static Analysis** - **Bias Off State Checks**: Analyze the design to ensure that power-gated domains are correctly biased off when required. - **State Transition Verification**: Verify that transitions to and from the bias off state are managed correctly, preventing unintended power leakage. #### **2. Dynamic Simulation** - **Power Down Scenarios**: Simulate various power down scenarios to assess the impact on system functionality and ensure proper bias off state management. - **Power Consumption Analysis**: Monitor power consumption during bias off states to identify any irregularities or inefficiencies. ### **Best Practices for Managing PG Bias Off States** 1. **Clear Power Management Strategy**: Develop a clear strategy for managing bias off states, including guidelines for when and how components should enter and exit these states. 2. **Continuous Validation**: Regularly validate bias off state implementation throughout the design process to catch and address issues early. 3. **Collaborative Approach**: Work closely with power management and system design teams to ensure that bias off states are integrated seamlessly into the overall design. 4. **Advanced Tool Utilization**: Use advanced tools like Synopsys VSLP for automated detection and correction of bias off state issues. #workwithuppula #synopsys #VSLPTool #powerefficiency Thanks, Vishnu

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A Look Back at 2024: Highlights and Achievements 1️⃣ Started a VLSI community VLSI TECH with Anoushka with a motive to motivate students in Vidharbha region to strengthen the pillars of technology (Semiconductor Industry). 2️⃣ Became a finalist in the India-Japan Hackathon(Selected among top 50 teams) with innovative transport solution! 3️⃣ Completed various programs with VLSI System Design Like NASSCOM VSD SoC Design Program & RISC V internship not only this also worked as a Teaching Assistant for Nasscom VSD SoC design program. 4️⃣ My YouTube channel took off—growing to 1.1k subscribers in just 4 months, and we're only getting started. 5️⃣Became a RISC-V International member and actively attended RISC-V Academia and training meetings. 6️⃣ Successfully completed 2 months training program by NIELIT on HLS programming. 7️⃣Created and shared content on RISC V ASM,System Verilog,UVM, AMBA protocols Verification & PCI Express. 8️⃣ Became a intern at COVERIFY and worked on AXI Verification IP with eUVM. 9️⃣ Secured the 1st spot in Namaste FPGA Technologies Top Learners of the Month for September. 🔟 Secured 3rd Position at College Chess Branch cup. Here's lessons I learned in 2024: 🤝 Sharing knowledge creates a richer community. 📚 Organization simplifies learning and improves accessibility. 🔗 Collaboration leads to innovative solutions in technology. 📝 Detailed documentation accelerates understanding in technical fields. 🛠️ Hands-on experience is invaluable for mastering complex topics. 📈 Continuous learning is essential in fast-evolving industries like VLSI. Every achievement has pushed me to new heights! 🚀 Get your free LinkedIn unwrapped from cleve.ai/unwrapped. #LinkedinUnwrapped #CleveAI

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"Every vote counts, Let your voice be heard! So vote for the future and choose VLSI for your career nurture".Our new VLSI batches are starting from May 20th. Register now by visiting us at www.sumedhait.com. #ElectionDay #YourVoteMatters #sumedhait #elections #voting #votingright #pd #dv #cl #physicaldesign #designverification #analoglayout

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Semiconductors are the backbone of modern technology, but have you heard about VLSI? Prepare to be amazed by the evolution of telecom industry with #TechFacts⚡️ Department of Telecommunications ( DOT ) #didyouknowfacts #facts #semiconductors #vlsi #telecom

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3 books to Master Artificial Intelligence in VLSI design 🚀 Machine Learning Techniques for VLSI Chip Design The books covers hardware architecture implementation, the software implementation approach, the efficient hardware of machine learning applications with FPGA or CMOS circuits, and many other aspects and applications of machine learning techniques for VLSI chip design. 🚀 Machine Learning in VLSI Computer-Aided Design This book provides readers with an up-to-date account of the use of machine learning frameworks, methodologies, algorithms and techniques in the context of computer-aided design (CAD) for very-large-scale integrated circuits (VLSI). Coverage includes the various machine learning methods used in lithography, physical design, yield prediction, post-silicon performance analysis, reliability and failure analysis, power and thermal analysis, analog design, logic synthesis, verification, and neuromorphic design. 🚀 Machine Intelligence in Design Automation: This brief booklet presents a hands-on approach for solving electronic design automation problems with modern machine intelligence techniques. By including step-by-step development of commercial grade design applications including resistance estimation, capacitance estimation, cell classification and others using dataset extracted from designs at 20nm, the book takes you the new journey of AI integration in VLSI. A detailed post is in the comments.

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Much like Vijay meticulously devising an escape plan based on the jail map in "Kathi," VLSI engineers craft a strategic floorplanning strategy to ensure optimal chip design. Just as Vijay considers various factors such as routes and obstacles, VLSI engineers meticulously plan chip layouts, balancing considerations like routing efficiency, power distribution, and area constraints. Both endeavors require careful analysis and planning to achieve their respective goals efficiently and effectively.#vlsi #chipdesign #floorplanning #optimaldesign #engineeringstrategy https://vlsifirst.com

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AXI is a multi channel bus which is popularly used as an interfacing protocol between multiple IP's and is useful both in RTL design and ASIC Verification. Below are the key concepts which are needed to understand AXI protocol in depth. [1] Difference between AXI and AHB. Number of Channels used in AXI. Why there is no separate Read response on AXI. [2] What are out of order and outstanding transaction in AXI. [3] What is the address boundary that slave can access in AXI. [4] Transfer mechanism for Write / Read with / without delay. [5] Valid and Ready hand shaking mechanism. What is deadlock condition. How to overcome it. [6] Difference b/w Incrementing and Wrapping Burst. What is a Fixed Burst type. [7] Difference b/w Bufferable and Cacheable type of transaction in AXI. [8] Complete understanding of Exclusive access phenomenon. Difference b/w OKAY and EXOKAY response. [9] What is a Locked access in AXI3. Why it is removed in AXI4. [10] What are the conditions for SLVERR and DECERR. [11] What is a QOS support for AXI4. What are the significance of AxREGION and AxUSER in AXI4. [12] Difference b/w AXI3 and AXI4. [13] What is a write interleaving method in AXI3 and why it's removed in AXI4. #vlsi #asic #semiconductorindustry #electricalengineering

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🚀 Analog VLSI: The Silent Powerhouse Driving Quantum Computing 🧑‍💻 In the rapidly evolving landscape of Quantum Computing 🌐, where qubits, entanglement, and superposition are the buzzwords, there's an unsung hero that's playing a pivotal role—Analog VLSI. Let's delve into how Analog VLSI is contributing to this cutting-edge technology and why it's indispensable! 🔍 #1️⃣ The Foundation of Precision Quantum computing relies on the manipulation of quantum states, which demands ultra-precise control over signals. 🎛️ Analog VLSI circuits excel in generating and processing continuous signals with high fidelity, enabling the precise control needed to manipulate qubits effectively. Without this precision, the delicate quantum states could easily be disrupted, leading to computational errors. ⚠️ #2️⃣ Bridging the Classical-Quantum Divide One of the challenges in quantum computing is the interface between classical and quantum domains. Analog VLSI provides a seamless bridge 🌉 by enabling efficient data conversion and signal processing. Through high-speed Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs), it translates quantum information into classical data formats, allowing for effective monitoring, control, and error correction in quantum systems. 🖥️ #3️⃣ Power Efficiency at Its Best In quantum computing, maintaining qubit coherence requires low temperatures, often near absolute zero ❄️. This poses significant challenges in power management. Analog VLSI circuits are inherently power-efficient, ensuring minimal thermal noise and heat generation. This efficiency is crucial in maintaining the delicate balance required for qubits to function properly over extended periods. 🕒 #4️⃣ Real-Time Signal Processing Quantum computers require real-time signal processing to maintain qubit coherence and perform operations swiftly. Analog VLSI, with its fast response times and low-latency signal processing capabilities ⏱️, is key to ensuring that quantum operations are executed with the speed and accuracy required for practical applications. #5️⃣ Scalability and Integration As quantum computing scales up, the integration of numerous qubits and control circuits becomes complex. Analog VLSI offers high-density integration capabilities, allowing for the compact design of quantum processors. This integration is critical in developing scalable quantum systems that can handle more qubits and deliver higher computational power. 📈 #6️⃣ The Future Outlook The fusion of Analog VLSI with quantum computing technology is paving the way for new frontiers in computing power and efficiency. As we advance toward practical quantum computers, the role of Analog VLSI will only grow more prominent, becoming the backbone that supports the next wave of technological breakthroughs 🌍. Follow Soumick Majumdar for more such technical content. Happy Connecting !!! #QuantumComputing #AnalogVLSI #VLSI #iiitb #gate #gate2025 #innovation

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Hello Linkedin Family I am starting a series.... 100 days 200 analog layout interview questions for a fresher.... I Hope these questions help many freshers... 1) what is the sub threshold Voltage in MOSFET......? Answer.....👇👇👇 Subthreshold voltage in a MOSFET refers to the gate-source voltage (VGS) that is slightly below the threshold voltage (VT), typically around 50 mV less than VT. In this region, the device exhibits exponential current behavior rather than the quadratic relationship seen in saturation, allowing for lower power consumption and improved performance in digital applications #mosfet #vlsi #vlsifreshers #freshers #analoglayout #questuins

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Insightful Expert Talks on VLSI

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Hi Everyone Today we will discuss about Crosstalk Crosstalk: It occurs when there are parallel running nets of same metal layer for long distance. When a signal on a net switches very fast then, the wires in its surroundings tends to switch too and their logical values or transition can be affected. This is called cross talk. It causes noise bumps in non-switching nets and advancing/delaying of transition in switching nets. They are 2 different types of crosstalk 1)Crosstalk Noise: -->It is undesired change in the logical values of victim due to switching in the input of aggressor. -->If one net is switching and other is at a constant value, the switching net may cause voltage spikes on other net.This is called as cross talk noise. -->Cross talk noise is evolving as a key source in degrading performance and reliability of high speed integrated circuits. 2)Crosstalk Delay: When there is some delay or advancement in output transition of victim due to input transition of aggressor, it is called as cross talk delay. It occurs when some transition is happening in both the nets.Cross talk delay depends on the switching direction of the aggressor and victim nets. # If input transitions in aggressor and victim occur in same direction then output transition of victim becomes faster and it is earlier. It may cause hold violations. ## If input transitions occur in opposite directions then output transition of victim becomes slower and it is delayed, which may cause setup violations. • Ways to fix Crosstalk effects -->Assign Non default routing (NDR) rules by Increasing the spacing. -->Insert buffer to split the long nets -->Jump to different metal layers -->Shielding - Ground lines run in between the signal lines so that they form coupling capacitance with ground. -->By up-sizing the driver of victim net or downsizing driver of aggressor net. Thank you Everyone #Happy learning #Physical Design #VLSI #Semiconductor.

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Just a thought RTL Design has few logics which is not required as per the design specifications, this portion of code gets excluded in code coverage analysis. By knowing this fact we still synthesis the logic and it increases the gate counts. but functionaly this logic has no use. Now can this be a area for AI based tool to discard that portion of logic during synthesis and we reduce the gate count?

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It's been a great walk through into the Innovus clock concurrent optimisation flow which deals with how to balance skew,how to achieve minimum skew and latency, how to use commands to create groups and balance the tree, different clock tree structures and the difference between each tree. #cadence #innovus #ccopt

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In 100 days 200 analog layout interview question series.... second question.... #AnalogLayout #ICDesign #Semiconductor #VLSI #LayoutDesign #EngineeringInterviews #AnalogDesign #ChipDesign #CircuitDesign #IntegratedCircuits #ElectronicsEngineering #EngineeringJobs #JobInterviewTips #TechnicalInterviews

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Hello Connections Click on the below link to understand PCIe Config Space and visit the channel to see other videos related to PCIe protocol. Subscribe to my YouTube channel for more such informative videos. https://lnkd.in/grYJmusS

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Hello LinkedIn Family In 100 days 200 analog layout interview questions series... Day 8..... Q16. why polysilicon used for gate in mosfet rather than metal ..? Ans.... 👇👇 👇 Polysilicon is preferred for MOSFET gates over metal due to its ability to support "self-aligned gate processes", which minimizes alignment issues and parasitic capacitance. Additionally, polysilicon can be heavily doped to achieve desired electrical properties, enhancing device performance and stability at high temperatures. #100DaysChallenge #InterviewPreparation #CareerDevelopment #JobInterviews #InterviewTips #ProfessionalGrowth #LearningJourney #SuccessMindset #CareerAdvice #SkillBuilding #Networking #PersonalDevelopment #JobSearch #InterviewQuestions #CareerSuccess #ContinuousLearning #MentorshipMatters #Inspiration #LeadershipDevelopment #KnowledgeSharing #GrowthMindset #ProfessionalNetworking #InterviewSkills #CareerGoals #SelfImprovement #Empowerment #JobReady #FutureLeaders #Resilience #ConfidenceBuilding

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