Dinesh Maheshwari

Dinesh Maheshwari

San Jose, California, United States
7K followers 500+ connections

About

Accomplished C -Level senior executive with 30+ years of successful track record of…

Activity

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Experience

  • Groq Graphic

    Groq

    Mountain View, California, United States

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    Silicon Valley, CA

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    Montreal, Canada

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    Silicon Valley, CA

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    Silicon Valley

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    Geneva Area, Switzerland

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    San Francisco Bay Area

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    Montreal, Canada

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    San Francisco Bay Area

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    Tempe, AZ, USA

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    Dresden Area, Germany

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    San Francisco Bay Area

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    San Francisco Bay Area

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    San Francisco Bay Area

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    San Francisco Bay Area

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    San Francisco Bay Area

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    US, Italy, India

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    San Francisco Bay Area

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    San Francisco Bay Area

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    Bell Labs Campus, New Jersey, USA

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    Greater Boston Area

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Education

  • Indian Institute of Technology, Delhi Graphic

    Indian Institute of Technology, Delhi

    Activities and Societies: Soccer, Squash, Badminton, Roller-Blading, Theater

  • Corporate Finance - 3.98/4.0; Certificate # GVP8C3J77N
    Financial Accounting - 3.9/4.0; Certificate # D4CJX4KPSA
    Operations Management - 3.8/4.0; Certificate # 9UND6VBXJ3
    Marketing - 3.9/4.0; Certificate # LE8GQXJHKU

  • Neural Networks and Deep Learning - 4.0/4.0, Certificate # PL5PKP65KKD
    By Andrew Ng, Adjunct Professor, Stanford University; Co-founder, Coursera; formerly head of Baidu AI Group/Google Brain

  • Activities and Societies: Captain and Student leader of the entire school (grade 1 to grade 12 ); Soccer, Badminton, Photography, Theater

    Ranked 18th across all of India in "All India Senior School Certificate Examination (AISSCE)"

  • Activities and Societies: Captain and student leader of Ashoka House ( 1 of 4 student houses of the school); Soccer, Badminton, Photography, Theater, Sculpting, Sketching

    Ranked 17th in India in "All India Secondary School Examination" (AISSE)

Publications

Patents

  • Memory devices and methods for high random transaction rate

    Issued US 8,630,111

    Other inventors
    See patent
  • Multi-port memory devices and methods

    Issued US 8,595,398

  • Memory devices and methods for high random transaction rate

    Issued US 8,570,790

    Other inventors
    See patent
  • Block mapping circuit and method for memory device

    Issued US 8,230,167

  • Methods for logically combining range representation values in a content addressable memory

    Issued US 8,122,189

  • Providing hardware independence to automate code generation of processing device firmware

    Issued US 8,069,436

    Other inventors
    • Ogami; Kenneth
    • Hastings; Mark
  • Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory

    Issued US 8,060,708

    Other inventors
  • Bridge device with page-access based processor interface

    Issued US 8,037,228

    Other inventors
    • Rajamanickam; Jagadeesan
  • Ternary content addressable memory (TCAM) cells with low signal line numbers

    Issued US 8,018,751

    Other inventors
  • Content addressable memory (CAM) cell having column-wise conditional data pre-write

    Issued US 7,813,155

  • Partial row expansion by logically combining range representation values in content addressable memory

    Issued US 7,814,266

  • Row expansion reduction by inversion for range representation in ternary content addressable memories

    Issued US 7,814,268

  • Multiprocessor system having an input/output (I/O) bridge circuit for transferring data between volatile and non-volatile memory

    Issued US 7,730,268

    Other inventors
  • Ternary content addressable memory (TCAM) cells with low signal line numbers

    Issued US 7,570,503

    Other inventors
  • Soft priority circuit and method for content addressable memory (CAM) device

    Issued US 7,474,545

  • Content addressable memory (CAM) cell having column-wise conditional data pre-write

    Issued US 7,450,409

  • Method and device for limiting current rate changes in block selectable search engine

    Issued US 7,447,052

  • Priority encoder circuit and method

    Issued US 7,436,688

  • Content addressable memory device

    Issued US 7,417,882

  • Two-stage gain equalizer

    Issued US 7,391,973

    Other inventors
    • Corrigan; Robert W.
  • Row expansion reduction by inversion for range representation in ternary content addressable memories

    Issued US 7,366,830

  • Automatic built-in self-test of logic with seeding from on-chip memory

    Issued US 7,346,823

    Other inventors
  • Content addressable memory cell configurable between multiple modes and method therefor

    Issued US 7,324,362

  • Content addressable memory (CAM) cell with single ended write multiplexing

    Issued US 7,298,635

  • Content comparator memory (CCM) device and method of operation

    Issued US 7,251,147

  • High contrast tilting ribbon blazed grating

    Issued US 7,057,819

  • Optical switch cascading system and method with fixed incidence angle correction

    Issued US 7,013,058

  • Arbitrary phase profile for better equalization in dynamic gain equalizer for optical communications

    Issued US 6,987,600

  • Cascading optical switch multi-plane system and method

    Issued US 6,983,087

  • Chirped optical MEM device

    Issued US 6,934,070

    Other inventors
    • Trisnadi; Jahia
    • Corrigan; Robert W.
  • Tilt-able grating plane for improved crosstalk in 1.times.N blaze optical switches

    Issued US 6,927,891

  • PDL mitigation structure for diffractive MEMS and gratings

    Issued US 6,922,273

    Other inventors
  • Tunable phase grating with optically linearized response

    Issued US 6,922,271

  • Method and apparatus for leveling thermal stress variations in multi-layer MEMS devices

    Issued US 6,922,272

    Other inventors
  • Blazed grating light valve

    Issued US 6,896,822

    Other inventors
  • Cascading optical switch three dimensional switch fabric system and method

    Issued US 6,870,982

  • System and method of acquiring delay, setup and hold values for integrated circuit cells

    Issued US 6,854,102

  • Optical switch cascading system and method with variable incidence angle correction

    Issued US 6,853,762

  • Diffractive light modulator with dynamically rotatable diffraction plane

    Issued US 6,829,077

  • Blazed grating light valve

    Issued US 6,829,092

    Other inventors
  • Patterned diffractive light modulator ribbon for PDL reduction

    Issued US 6,806,997

    Other inventors
  • Method and apparatus for measuring wavelength jitter of light signal

    Issued US 6,785,001

  • Method and/or software for determining the capacitance of an analog/mixed signal circuit

    Issued US 6,775,627

    Other inventors
    • Liu; Zhiwu
    • Boes, II; Barry A.
  • First-in-first-out (FIFO) memory devices and methods having multiple queuing

    US 9,465,576

  • Memory devices and methods having multiple address accesses in same cycle

    US 9,576,630

  • Memory devices and systems including cache devices for memory modules

    US 9,390,783

  • Multi-channel physical interfaces and methods for static random access memory devices

    US 9,224,454

  • Multi-channel, multi-bank memory with wide data input/output

    US 9,361,973

  • Multi-port integrated circuit devices and methods

    US 9,489,326

Languages

  • English

    Native or bilingual proficiency

  • Hindi

    Native or bilingual proficiency

  • Italian

    Limited working proficiency

  • Machine Hardware languages - Verilog, VHDL

    Full professional proficiency

  • Machine Software languages - C/C++, Pascal, ADA, LISP, Fortran, Java, Python

    Full professional proficiency

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