Satya Raviteja Erpina

Just a thought RTL Design has few logics which is not required as per the design specifications, this portion of code gets excluded in code coverage analysis. By knowing this fact we still synthesis the logic and it increases the gate counts. but functionaly this logic has no use. Now can this be a area for AI based tool to discard that portion of logic during synthesis and we reduce the gate count?

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To my friends in India who are asking where they can get a copy of “Next Level Testbenches: Design Patterns in SystemVerilog and UVM:” My understanding is that KDP (Kindle Direct Publishing, the publishing arm of Amazon) does not have a print on demand plant in India. Instead, Amazon India buys books from distributors in the US and the UK and resells them in India. However, they only buy paperback books, not hardcover books. So, I put together a paperback edition with identical content as the hardcover edition. The paperback edition launched this week on Amazon with “extended distribution,” which gives permission to be sold through international distributors. I don’t know when it will reach the Indian market. The KDP website says it could take up to eight weeks to get through the distribution network. In the meantime, it’s available on amazon.com, amazon.uk, and other European markets. I’m still learning how the international publishing market works. Thank you for your patience. P.S. Ebooks were not in my original plans. There are some challenges converting a book formatted for print into an ebook. I’ll look into it, but cannot promise an ebook edition will be available.

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Basic and Simple Blueprint to structure a project in UVM [Important for VLSI Professionals] UVM is a preferred verification language due to its reusability, scalability, interoperability, CRV, proper phasing, etc. Below are the most simplest basic steps mentioned as how to develop a TB infrastructure from scratch. Step 1: Documentation ✓ Go through the specification thoroughly and prepare the Verification Plan, Test Plan, Assertion Plan and understand the working of the IP or protocol. Step 2: Coding ✓ Code the interface by listing all the I/O port. Code the Clocking block to avoid race condition, synchronization and direction to TB. Optionally code the Modport. *** Note: Cautiously use the input / output skew and the clockvar There are certain rules while using the Clocking block and modport which someone needs to follow. **** ✓ Code the transaction class and use the randomization wherever applicable. Try to avoid the field macros and instead use proper methods. **General thumb rule the input should be rand. Moreover try to use the do_copy, do_ compare, convert2string, do_print methods instead of using field macros which has a overhead** ✓ Code the driver logic for the pin level activity at DUT. Use sequencer driver handshake properly depending on pipelined / non pipelined access. *** Use proper coding guidelines while coding driver logic *** ✓ Code the Sequencer and use arbitration mechanism if needed. ✓ Code the Monitor to handle the transaction. The analysis port first needs to be connected to Agent and then to other subscribers like scoreboards, etc. ✓ Build the agent and give proper instantiation for Driver, monitor, and Sequencer. Depending on application the Agent can be chosen as either active or passive. ✓ Code the env class and give proper connection. ✓ Write some basic sequence items to check the flow along with base test class. While coding the sequence items number of methods can be used to execute the sequence. ** While using the sequence use start_item/finish_item instead of `uvm_do macro ** ✓ Code the scoreboard either with the help of tlm fifo, associative array, queue depending on whether it's used in order or out of order comparator. The coding style will change depending on need. ** While designing the Scoreboard make sure the predictor and evaluator are separate** There are almost 6 to 7 different methods of designing a scoreboard ✓ Code the top module and use of run_test and set the config db. *** Above are some of the very basic steps mentioned but ideally the testbench will be complex and use many more concepts which are not mentioned above. Some of them are: ✓ Virtual Sequencer and Virtual Sequences. ✓ RAL ✓ Callbacks ✓ Objection mechanism ✓ Config and resource db ✓ Coverage ✓ Assertions #vlsi #asic #electronics #electricalengineering

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Below is a very basic Mesh structure that we encounter in VLSI Industry. Let me decode this architecture. There are 25 nodes in the Diagram. A node can be visualized as anything, it can a capacitor or CPU core, or Networking core. So if we assume the node as ARM CPU core this architecture becomes the basis for a Server Class Super Computer with 25 cores. Whereas if we assume the node as Marvell Networking ASIC (25 routers) this architecture becomes the basis for a Networking fabric which are deployed in your offices, Airports, Datacenters, Colleges etc. The way we visualize, the context changes completely. This is the beauty of Chip Designing. There may be difficulties to enter the VLSI industry, However, if you put your heart and soul and work hard You will have billions of ways to explore this Exciting Field. Welcome to VLSI Industry #chipdesign #vlsi #india #marvell #arm

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Qualcomm vs Arm Qualcomm's central processors are properly licensed under an agreement with Arm Holdings jury found. Arm's (O9Ty.F), shares were down 1.8% in extended trading after the news, and Qualcomm's (QCOM.O), shares were up 1.8% #Qualcomm #Arm #chip #licence #Nuvia

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On Day 45 of my 100 Days of RTL Coding, I focused on converting an SR flip-flop into a T flip-flop using Verilog. This conversion required reconfiguring the logic to achieve the toggling functionality of the T flip-flop while ensuring the Set and Reset inputs were appropriately utilized. Through this process, I deepened my understanding of flip-flop functionality and the relationships between different types of sequential circuits. Looking forward to more challenges and learning ahead! #RTL #Verilog #DigitalDesign #FlipFlop #100DaysOfRTL #Day45 Here's my GitHub link : https://lnkd.in/gTfwFrhw 

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🚨 Calling all Graduates! NVIDIA released its New Grad ASIC Verification Engineer role. Here's what you need to know: ⚙ Located in Santa Clara, CA ⚙ Full-time pay is ~$92,000-$180,000/yr ⚙ Full-time(40hrs/week) So if you have And have experience in SystemVerilog, C and/or C++, Python and/or Perl Then consider applying to NVIDIA now! Here's the link 👇 https://lnkd.in/gK7MNtDW You got this! ＿＿ Found this useful? Consider re-sharing 🔁 and following me Mark Benliyan for more content like this! #newgrad #nvidia #coding #softwareengineering

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#fundamentalseries UVM Monitor Classes 7. uvm_monitor * Observes DUT signals and converts them into transactions. * Sends transactions to other components like scoreboards and coverage collectors. * Passive component, does not drive signals. Environment Classes 8. uvm_env * Container class for grouping related UVM components (e.g., agents, scoreboards). * Typically represents a complete verification environment for a specific DUT. Agent Classes 9. uvm_agent * Groups related driver, sequencer, and monitor components. * Can be active (contains a driver and sequencer) or passive (contains only a monitor). Reporting Classes 10. uvm_report_object * Provides reporting utilities for printing messages, warnings, and errors. * Base class for components that need reporting capabilities. 11. uvm_report_server * Centralized reporting mechanism. * Collects and processes messages from uvm_report_object instances. Scoreboard and Analysis Classes 12. uvm_scoreboard * Analyzes DUT outputs and compares them with expected results. * Receives transactions from monitors via analysis ports. 13. uvm_analysis_port * Used for broadcasting transactions to one or more analysis components. * Example: uvm_analysis_port #(T)where T is the transaction type. 14. uvm_analysis_imp * Implements the analysis export interface. * Used to connect analysis ports to scoreboards or other analysis components. #uvm #uvmmethodology #fundamentalseries #uvmconcepts #uvmsyntax #verification #testbenches #verificationengineer #training #mirafratechnologies

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I come across multiple folks every year who want to switch job profile. It becomes difficult to switch after 2 years if person is not ready to relocate and compromise with salary. This is one of the reasons I recommend students to try embedded software career path first. I have conducted several surveys in LinkedIn for awareness purpose. Learning firmware or embedded software will definitely add value to PCB design background folks. Experienced folks can explore management role after firmware development skills. We have many hardware background folks in our Developer kit community. They got better opportunities after learning firmware programming. Our Ultra kit (Six months live session) can definitely help such folks due to several features: a: Learn C in various levels starting from Level 1. It depends on various types of C used in embedded software development. It includes logic building and project based hands-on approach. We have enough testimonials of C skills improvement in both students and working professionals. b: With longer duration, we can provide learning material for various architectures, RTOS, Linux and testing as well. c: PCB design background folks can try to design complete product. We have provision for this as well based on my past experience. Answer : This is possible but the complete switch over to embedded software will take some time. There are several factors : 1: If you are from an ECE background, you might have studied Microprocessor and Digital Electronics. If not, you have to study these two first. 2: You have to work on your C skills and learn firmware development with ARM based MCU. 3: If your current CTC is above 14 LPA , you have to first try to find firmware development in your organization. 4: You may also explore the team lead kind of role where you get some opportunity to work in firmware development.. 5: RTOS and Linux Application development can add value to your profile. 6: You have to be flexible for relocation. 7: Learning firmware development will definitely add value to your profile even if you don't get an immediate opportunity to switch. Answer to I have been working as PCB's design engineer for the past 7 years. I would like to switch over to the embedded software field. Is it possible? by Sanjay Kumar https://lnkd.in/gWtyirVq #embedded #opentowork #pcbdesign #embedkari

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If you are new to Formal Verification, I have 3 articles on systemverilog.io to get you started. 1. 𝗦𝗩𝗔 𝗯𝗮𝘀𝗶𝗰𝘀 - Will build the necessary foundation in SVA, with lots of examples 2. 𝗔 𝗴𝗲𝗻𝘁𝗹𝗲 𝗶𝗻𝘁𝗿𝗼𝗱𝘂𝗰𝘁𝗶𝗼𝗻 𝘁𝗼 𝗙𝗼𝗿𝗺𝗮𝗹 𝗩𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻 - What is Formal, how is it different from Functional Verification. 3. 𝗔 𝗯𝗹𝘂𝗲𝗽𝗿𝗶𝗻𝘁 𝗳𝗼𝗿 𝗙𝗼𝗿𝗺𝗮𝗹 𝗩𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻 - End-to-end strategy for someone new to Formal Link: https://lnkd.in/gZTBX46K These were written in 2019, but is still a good place to start. If you have a Synopsys SolvNet account, you can also watch a talk I gave in SNUG 2019. ~~~ Join 1500+ readers in my upcoming newsletter: svio.link/newsletter #verilog #systemverilog #formalverification #asic

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How to start focussing and preparing for Semiconductor and AI from 2nd year of Engineering in ECE / EEE / CSE: [1] Mathematics: Not only essential for ML and VLSI but helps in Quantum Computing as well. Key concepts: a. Probability and Statistics - Bayes theorem, variance, standard deviation, Distributions, Regression, Bias, etc. b. Linear Algebra - Eigen values, Eigen vectors, Matrix operations. c. Complex Number - Complex Plane, Polar and exponential form, Fourier transform, Euler and De Moivre's theorem, Conjugate. [2] Digital Electronics: The most basic and fundamental subject for VLSI. Key Concepts: Boolean Algebra, Combinational and Sequential Circuit, FSM, Static Timing Analysis. Not covering in depth since already covered in earlier posts. [3] Analog Fundamentals: Key concepts: a.BJT, MOSFET, CMOS, Problems on CC, CE, CB, CS, CG and CD. b. Current Mirror, Amplifier, Oscillator, Implementing stick diagrams of basic gates and custom circuits, Drain calculation, triode and saturation region. [4] Algorithms: This subject is not essential and mandatory but when I look back i personally feel that this subject is a necessity to increase the intuitive thinking and problem solving approach. Key concepts: a. Divide and Conquer, Greedy, Dynamic Programming, Sorting and Searching, travelling Salesman, Dijkstra's, kruskal, etc. b. Complexity theory - P, NP, NP Hard and NP Complete. [5] HDL Coding: Verilog - Coding guidelines, Syntax and Semantics, Coding structure. The best way to learn is to start implementing the digital blocks like multiplexer, flip flops, basic gates, counters. If you don't have any tool use edaplayground. [6] Python: Libraries: Pytorch, pyuvm, NumPy, SciPy, scikit-learn. [7] Machine Learning: Key concepts: a. Supervised, Unsupervised, Reinforcement, Neural Networks, Gradient Descent, Deep learning, Back propagation. b. Frameworks like TPU and PyTorch. [8] SystemVerilog: a. Data types, Interface, Clocking Blocks, Modport, Virtual interface, Synthesizable and Non Synthesizable construct, Testbench infrastructure. [9] Protocols: AHB, APB, FIFO to start with. Interconnect the two domains of VLSI and AI by leveraging ML for Automation in Semiconductor and debug the Chip faster. #vlsi #asic #electricalengineering #electronics

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Important methods in Digital Design to optimize Boolean logic in VLSI: To minimise or optimise the Boolean expression of digital logic theorems and laws related to digital logic or K-map, reduction techniques should be adopted as per the need. When the number of variables are four in a sop or pos expression, k map can able to reduce them easily. Even upto five variable and maximum upto 6 variables K map can able to perform quite efficiently. For 5 variable(ABCDE), 32 combinations are possible so two blocks of 4 variable k map are built from (0 to 15) and (16 to 31) and for BCDE, A is taken for both 0 and 1. For 6 variables, 64 combinations are possible, so mapping is done on the basis of four, four variable k map. But beyond that k map technique fails to meet the demand. So here comes the tabulation method. ✓ Tabulation method: Tabulation method in digital logic is necessary to optimise the Boolean expression when the number of variables are large, to be more precise more than six. There are two approaches to this. [1] Variable Entered Mapping (VEM) : VEM is just an extension of the K map approach where a dummy variable is AND ed with each of the minterm or the maxterm of the expression for either assertion or de assertion. That particular dummy variable can be customised according to needs and can be either on and off . Instead of filling up the mappings with corresponding 1's and 0's, VEM contain function of variables. [2] Quine-McCluskey Method: This is a another tabular method and is particularly used when both K map and VEM approach fails. The concept behind Quine-McCluskey method is the combining method approach where AB(bar) + AB = A(B + B(bar)) = A. ✓ Combine all the minterm of the expression into a common group and to first find the prime implicants of the Boolean logic. ✓ Group the prime implications and from that deduce the essential prime implicants by constructing table. ✓ Further from the essential prime implicants reduce it further to another set of essential prime implicants. ✓ Remove the earlier prime implicants where it only remained with the rows and columns with maximum number of minterm and maxterm. Drawbacks of QM method: a] Prime Implicants grows very huge making the solution space quite large. b] Difficult to generate all PI. [3] Petrick's method: It eliminates the problem of QM method, by reducing or eliminating the EPI rows and columns. [4] Espresso: It produces a minimized table which is very useful for Synthesis of the digital logic. ✓ Other important methods: [1] Consensus theorem: It helps to reduce the redundant terms from the Boolean description. [2] Binary Decision Diagram (BDD): Optimises an expression by factoring into either 0/1 and then decide which path to move. [3] Flattening / Factoring: They are the method to optimise an unoptimized RTL description. #vlsi #asic #electronics #electricalengineering

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#fundamentalseries UVM UVM is a methodology to verify the design or the RTL. It is built on top is System Verilog and provides a set of base classes, methods functions which can be reused and maintained. The flow is as follows - Define the base classes which form the foundation of a UVM testbench - Factory And configuration helps to create objects dynamically and are flexible and can be reused. Configuration helps to set the parameters between different components of the testbench - Phases helps in the order of operations during simulation three main phases which is again subdivided - TLM these are the communication between components which enables for easy integration Have a great day #uvm #uvmmethodology #fundamentalseries #uvmconcepts #uvmsyntax #verification #testbenches #verificationengineer #training #mirafratechnologies

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NVIDIA is seeking best-in-class ASIC Verification Engineer to verify the world’s leading GPUs. In this role, you will be doing unit level verification of the process scheduling and system interface hardware of the GPU. This position will be working across many #NVIDIA teams from software, to architecture, design, methodology, and more. The GPU is used in applications from consumer graphics, through self-driving cars, to artificial intelligence, all of which you will be involved in and learn about. #electricalengineering #computerengineering #computerarchitecture #asic #verification #systemverilog #testbench #debugging #uvm

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Recently, Apple has launched the iPhone 16 series, enabling WiFi 7 for iPhone users. Let us do some brief system-level calculations to understand noise and ADC requirements.   Assumptions: Modulation Scheme: 4096-QAM Channel Bandwidth: 320 MHz Received Power (P_RX): -50 dBm Front-end RX Gain ( G ): 25 dB Front-end Noise Figure ( NF ): 10 dB Thermal Noise Power Density ( N_0 ): -174 dBm/Hz Step 1: Thermal Noise Power Calculation The noise power density is a function of thermal noise at room temperature (290K). Given the bandwidth B = 320 MHz, the total noise power over the bandwidth is: N_total = N_0 + 10log10(B) N_total = -174 + 85.05 = -88.95 dBm Step 2: Adjust for Noise Figure by Front End The receiver’s noise figure (NF) adds noise to the system. Adjust the total noise power by the noise figure: N_output = N_total + NF N_output = -88.95 dBm + 10 dB = -78.95 dBm This represents the total noise power at the output of the front end. Step 3: Signal Power at the ADC Input The signal power at the input of the ADC is the received power amplified by the front-end gain (G = 25 dB). P_ADC_in = -50 dBm + 25 dB = -25 dBm Step 4: Signal-to-Noise Ratio (SNR) Calculation The SNR at the ADC is the difference between the signal power at the ADC input and the total noise power at the output: SNR = P_ADC_in – N_output SNR = -25 dBm - (-78.95 dBm) = 53.95 dB This is the SNR at the input of the ADC. Step 5: Determine the ADC Resolution (ENOB) The effective number of bits (ENOB) of the ADC can be determined from the SNR using the relation: SNR = 6.02 x ENOB + 1.76 dB ENOB = (SNR - 1.76) / 6.02 ENOB = (53.95 - 1.76) / 6.02 = 8.67 bits Step 6: Verify SNR Requirement for 4096-QAM For 4096-QAM, the required SNR can be approximated by: SNR_required = 10log10(M), where M = 4096 for 4096-QAM SNR_required = 10log10(4096) = 36 dB Since the calculated SNR at the ADC input (53.95 dB) exceeds the required SNR for 4096-QAM (36 dB), the system is well within the acceptable range for decoding the signal. Step 7: ADC Full-Scale Dynamic Range To ensure proper ADC operation, the full-scale range of the ADC should encompass both the noise floor and the signal power. The total noise power at the ADC input: N_output = -78.95 dBm The signal power at the ADC input: P_ADC_in = -25 dBm Thus, the required dynamic range (difference between the signal and noise) is: Dynamic Range = P_ADC_in – N_output = -25 - (-78.95) = 53.95 dB The ENOB of 8.67 bits corresponds to a dynamic range DR = 6.02 x 8.67 = 52.2 dB This is close to the 53.95 dB SNR at the input of the ADC. Conclusion: For a typical WiFi 7 system with 4096-QAM and 320 MHz bandwidth: Required ADC ENOB: 8.67 bits. However, a nominal ADC resolution of 10 bits would provide adequate performance with design margins for implementation losses, ensuring the system can properly digitize the incoming signal. *Please note that Front End gain is a variable that also plays a crucial role in properly functioning WiFi Receiver.

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Today's focus was on implementing a Single-Port RAM in Verilog. This memory module allows for either a read or write operation at a given time, using a single port for addressing and data transfer. The design includes features such as address decoding, write enable control, and synchronous operation with a clock signal. Single-Port RAM is a fundamental building block in digital systems, widely used for temporary data storage in embedded systems and processors. Pleased to see the seamless integration of memory design into my RTL journey! #RTL #Verilog #SinglePortRAM #MemoryDesign #DigitalDesign #100DaysOfRTL #Day80 Here's my GitHub link : https://lnkd.in/gTfwFrhw 

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Recently I took up the R&D activity of Mode Merge technology.    Since it was only an evaluation my Lead suggested to take an IP which has been taped out.   I took SERDES 64Gbps chip. I started my Mode merging journey by manually adding all the necessary inputs. We had 2 Func modes both high speed and low speed which I wanted to merge into Single mode. Once I generated Merged SDC and ran STA to my surprise I saw timing was 100% correlated with original run. But when I saw the analysis coverage report it showed 100% untested, since it was a tapeout database both global timing reports were clean. Once I opened the merged SDC We saw some case analysis missing.   Upon investigation I see 2 more issues in the EDA tools that the Analog library that I took for reading had 5 modes ( 2 func + 3 scan ) even after giving func modes for merging I see the Merged Scenario is enabling all the modes due to which wrong Library setup time arc is being picked up, - for time being I manually added set_disable_timing to block scan related arcs to get picked by EDA tools.    In my evaluation I am able to achieve Timing correlation when I merge 2 func modes into 1 func mode.   Now I wanted to enable Mode merge technology in SERDES 112Gbps which was a production chip. My strategy was simple I wanted to merge 2 func modes ( high speed+low speed) into 1 mode and 3 scan modes ( at_speed, shift, capture) into 1 mode. Imagine our signoff strategy is every mode takes 10 scenarios ( 4 setup corners + 6 hold corners ). The target was to reduce 50 Scenarios to 20 Scenarios.   When I enable ECO tool report generation inside STA flow the runs are getting crashed. The main culprit was the set_sense command which gets dumped inside Merged SDC. To avoid tool crashes I tried to experiment with latest Tool version, However STA runtime is huge how are we going to reduce STA runtime? We came up with one more variable that can reduce set_sense arc size collection this helped us in dumping more set_sense commands due to which the number of lines increased in the file which is fine because STA tool has a multi threading feature to take care of.   We are able to achieve Merged STA Runtime on par with original SDC run and ECO tool runtime reduced 50% which is expected since reading 20 timing window files is more faster than reading 50 timing window files. Overall Disk space savings per Run was 50%. Mode merge technology helped us reduce 50 scenarios to just 20 scenarios.    Real time deployment took me 4 months of Hard Work and long hours of debugging helped us improve the Productivity of STA engineers.   Happy Learning.. 😊 #onemarvell#vlsi#sta#learnings

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