Kelsey Wooley

As the growth chart for gallium nitride (GaN) wafer demand is looking more like a hockey stick, it’s apparent that innovators who have long believed in the merits of GaN are being proven right. A private company in El Segundo, CA that predates some of the other startups in the GaN-based power IC space by more than a decade has been hard at work developing solutions in this space for over seventeen years. That company is EPC - Efficient Power Conversion and I got a firsthand look at some of their solutions when I was at the 2024 APEC Conference. They were co-founded in 2007 by a luminary of the power IC industry and CEO Alex Lidow. Lidow was at International Rectifier for over thirty years and had leadership positions spanning R&D and manufacturing. He was even their CEO for 12 years. As co-inventor of the silicon power MOSFET in the 1970s, his seminal work has shaped development in this sector. Lidow was flanked by Joe Cao and Robert Beach, both of whom have also made their own impact. Cao had over 15 years of experience and more than 30 patents in developing GaN and silicon power device technologies before deciding to embark on the quest with Lidow. Beach had founded multiple companies aimed at bringing GaN ICs to the marketplace before partnering with Lidow and Cao, making him a perfect complement to their triumvirate. What put EPC on the map was the development of their proprietary enhancement-mode GaN (eGaN) transistors which they released in June 2009. Unlike traditional MOSFETs, which used built-in channels between the drain and source, eGaN MOSFETS had no such channel. eGaN MOSFETs’ have small geometry, low power dissipation, and are easy to manufacture, making them desirable for a wide array of applications. The founders also had the foresight to manufacture using a foundry meant to produce silicon devices and were able to create a mature, efficient, and low-cost supply chain to bring new products to market quickly. Nowadays, newer companies in the space are gaining similar traction using this approach, but it’s safe to say EPC was a pioneer and began to reap the benefits decades ahead of competitors. This is another key element that differentiates them. In my experience, “mature startups” tend to be modest organizations, often letting their technology speak for itself and not over-indexing on marketing their brands to potential talent. But the hiring landscape is far more competitive than it was when they started and the allure of high-growth startups can be attractive for talented engineers. EPC’s goal is to enable companies to develop their technologies by leveraging the power of GaN and avoid being left behind by developing on silicon. That, combined with their lengthy market presence and leadership team, are strong elements to highlight and EPC would be well-served to fold these details into their talent attraction messaging. #semiconductorindustry #galliumnitride #powermanagement

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Learn about some recent research of Nanostructures using UV-Visible-NIR microspectrometers from CRAIC Technologies: https://lnkd.in/guh7fqyt #microscope #spectroscopy #Microscopy #spectrophotometer #spectrometer #nanotechnology

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CRAIC Technologies has created an review of some recent, interesting research in Materials Sciences using microspectrophotometers. Check it out here: https://lnkd.in/gq6hHu9U #spectroscopy #spectrophotometer #microscope #microscopy #science #Raman

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TSMC Advances Silicon Photonics Strategy: A Leap Towards Optical Era TSMC is making significant strides in silicon photonics, according to the Economic Daily News. Recent breakthroughs include integrating co-packaged optics (CPO) with advanced semiconductor packaging. Sample deliveries are projected for early 2025, with 1.6T optical transmission products expected in mass production by late 2025. Broadcom and NVIDIA are likely among the first customers. ◾ Key highlights include: ▪️ Successful trial production of the micro ring modulator (MRM) on TSMC's 3nm process, enabling CPO integration with HPC and AI ASIC chips. ▪️ Potential leap from electrical to optical signal transmission, addressing current limitations in speed and heat dissipation. ▪️ Challenges persist with CPO module packaging due to complexity and low yield rates, possibly leading to outsourced optical engine packaging. NVIDIA reportedly plans to adopt CPO for its GB300 chips (H2 2025) and Rubin architecture, aiming to enhance NVLink interconnect performance. These advancements position TSMC at the forefront of the optical computing era, reshaping the future of high-performance computing and AI applications. What are your thoughts on the potential impact of silicon photonics in AI and HPC? Share below! Thanks again to TrendForce Corporation for the full article with more background and insights click the source link in the comments below. #Semiconductors #SiliconPhotonics #AI #HPC #TSMC

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According to reports Qualcomm is likely to use UMC (note: another foundry) for its advanced packaging needs likely WoW (Wafer on Wafer) Hybrid bonding. Trial product likely starting in mid-2025 with full production expected in 2026.

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I’m excited to be the new owner of a state of the art molecular beam epitaxy (MBE) system currently set up for epitaxial Ga/Mn/As/Ge heterostructure growth .. I’ll be installing this bad boy in my old Virginia Cleanroom fab near Virginia Tech where I started my first silicon micro-machining and thin films company 30 years ago in a burnt down church- ACT MicroDevices. The clean room there never had such good company as this guy. I spent my first decade there (and at its sister facilities with our growth) working on silicon micro machining and micro optics for hybrid optoelectronics and their packaging - esp for integrated optics and advanced fiber optic applications like laser die wafer level hermetic packaging. In one project - I multilayer AR coated over 2 million sub millimeter discrete precision micro-optics for Lucent for fiber optic backhaul networks - for their “Laser 2000” program - a SiOB based laser transmitter. I ran it in a LPVCD tube furnace I modified. This ended up being the most profitable job I ever did though I bid it at cost to win the project. I was able to transition from 10k lenses in a batch to 60k in a batch in less than a year. Due to careful engineering of the coating layer stresses we ended up becoming their sole source at ~20 cents per lens. Why did coating stress engineering matter? This is because with sub-mm lenses on SiOB platforms you can’t use epoxy - they were solid state bonded to 3um Al deposited in a <111> inverted pyramid in the silicon chip at the 4 tangential contact points- the final layer compressive was key to high shear. Ok - Back to the “why” on the heteroepitaxial growth… high delta N ridge waveguide SOI integrated optics were always held back by needing to hybridly integrate lasers and detectors (Intel)… meanwhile GaAs / InP were just too expensive and fragile for complex and large integrated optical systems. Enter recently a new pioneer: heteroepitaxial Ge on Sapphire https://lnkd.in/gschJcuB follow by direct active layers … I’m now thinking -as the Mandalorian says -“this is the way” :) viz: Integated Microwave Photonic Circuits See: “Integrated microwave photonics” Nature Photonics volume 13, pages 80–90 (2019) https://lnkd.in/gAhxui35 For me - a marriage of my first love in optoelectonics (Si-Pak) with my second - advanced microwave/mm-wave circuits (PolyStrata) into something new, far smaller, more integrated and faster. Who wants to collaborate? I haven’t worked with big UHV ion pumps on MBE since high-school when I brought them home from the local tech junkyard with ln2 “sorption” pumps to rough your UHV chamber .. I always thought it was cool that you could use diminishing pump discharge current to measure your UHV degree of success - something that takes less energy the better it gets! What else takes less energy the better it gets 🤔 Photo of my new system below from the manufacturer. (racks of controllers not shown).

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TSMC 3nm chip output to rise over 300% in 2024, says fab director 🤯💡 #TSMC is scaling up its 3nm #chip output, which in 2024 will be over three times that of 2023, according to Y. K. Hwang, company senior director for Fab 18B. The #Taiwan session of TSMC's annual #technology symposium, held on May 23, followed the same theme as the North American session in April. Nonetheless, TSMC CEO C. C. Wei did not appear on stage for the Taiwan session. New faces such as Hwang shared additional details on the foundry's capacity development strategy and future fab projects. Hwang oversees TSMC's Fab 18B located at the Southern Taiwan Science Park (STSP), responsible for manufacturing 3nm chips. Hwang stated at the symposium in Hsinchu that TSMC is expanding its production capacity for 3nm technology; however, a shortage persists. To satisfy customer demand, the #foundry will further boost its production of 3nm #chips. A big thank you again to Monica Chen , Jessie Shen and DIGITIMES Asia for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/ewby8hnG #semiconductorindustry #semiconductormanufacturing #semiconductor #semiconductors #technology #tech #innovation #foundry #geopolitics #it #ai #aiot #automotiveindustry #consumerelectronics #datacenters #nvidia #apple #amd #intel #smartphones #cloudcomputing #hpc #pc

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TSMC: Performance and Yields of 2nm on Track, Mass Production To Start In 2025 💡 In addition to revealing its roadmap and plans concerning its current leading-edge process technologies, #TSMC also shared progress of its N2 node as part of its Symposiums 2024. The company's first 2nm-class fabrication node, and predominantly featuring gate-all-around transistors, according to TSMC #N2 has almost achieved its target performance and yield goals, which places it on track to enter high-volume manufacturing in the second half of 2025. TSMC states that 'N2 development is well on track and #N2P is next.' In particular, gate-all-around nanosheet devices currently achieve over 90% of their expected performance, whereas yields of 256 Mb #SRAM (32 MB) devices already exceeds 80%, depending on the batch. All of this for a node that is over a year away from mass production. Meanwhile, average yield of a 256 Mb SRAM was around 70% as of March, 2024, up from around 35% in April, 2023. Device performance has also been improving with higher frequencies being achieved while keeping power consumption in check. Thanks again to Anton Shilov and AnandTech for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eHgpfX4k #semiconductormanufacturing #semiconductors #semiconductor #tech #technology #innovation #chip #chips #integratedcircuits #ic #foundry #taiwan #geopolitics #asml #thenetherlands #europe #euv #computer

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Perhaps I didn't focus on it, but I hadn't seen any major news about US CHIPS Act money being spent on package, assembly and testing https://lnkd.in/gPZESgk5 TSMC and Amkor Technology, Inc. sign a deal to build advanced packing near TSMC's new fab in US, in Arizona If US wants complete Semiconductors manufacturing chain in the country, US will need facilities making the lowly QFN packages (even SOTs probably) - all these high-end chips are useless without the low end power and communication chips, and those need low end processing. It will be much harder to move that supply chain though, that supply chain is still quite a bit labour intensive.

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TSMC: Performance-Optimized 3nm N3P Process on Track for Mass Production This Year 🤩 With N3E already in volume production, #TSMC is reporting that they're seeing "great" yields on the second-generation 3nm-class process note. According to the company, the D0 defect density of N3E is at relative parity with N5, matching the defect rate of the older node for the same point in its respective lifecycle. This is no small feat, given the additional complexities that come with developing one last, ever-finer generation of #FinFET #technology. So for TSMC's bleeding-edge customers such as Apple, who just launched their #M4 #SoC, this is allowing them to reap the benefits of the improved process node relatively quickly. "N3E started volume production in the fourth quarter of last year, as planned," a TSMC executive said at an event. "We have seen great yield performance on customers' products, so they did go to market as planned." TSMC's N3E node is a relaxed version of N3B, eliminating some EUV layers and completely avoiding the usage of EUV double patterning. This makes it a bit cheaper to produce, and in some cases it widens the process window and yields, though it comes at the cost of some transistor density. Meanwhile, looking towards the immediate future at TSMC, N3P has finished qualification and its yield performance is close to N3E, according to the company. Thanks again to Anton Shilov and AnandTech for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/dkFujc2R #semiconductorindustry #semiconductors #technology #tech #innvoation #foundry #taiwan #chip #chips #icdesign #mobile #consumerelectronics #ai #datacenter #computing #computer #nvidia #amd #qualcomm #it #ml

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I am always amazed, how every part of these lithography machines has its own story and how technical requirements were overcome. IMHO it's the best R&D industry sector to be in right now. Which technological solution of a scanner amazes you?

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TSMC's 3D Stacked SoIC Packaging Making Quick Progress, Eyeing Ultra-Dense 3μm Pitch In 2027 TSMC's 3D-stacked system-on-integrated chips (SoIC) advanced packaging technologies is set to evolve rapidly. In a presentation at the company's recent technology symposium, #TSMC outlined a roadmap that will take the #technology from a current bump pitch of 9μm all the way down to a 3μm pitch by 2027, stacking together combinations of A16 and N2 dies. #TSMC has a number of #advancedpackaging technologies, including 2.5D #CoWoS and 2.5D/3D InFO. Perhaps the most intriguing (and complex) method is their 3D-stacked system-on-integrated chips (SoIC) technology, which is TSMC's implementation of hybrid #wafer bonding. #Hybridbonding allows two advanced logic devices to be stacked directly on top of each other, allowing for ultra-dense (and ultra-short) connections between the two chips, and is primarily aimed at high performance parts. For now, SoIC-X (bumpless) is used for select applications, such as AMD's 3D V-cache technology for #CPUs, as well as their Instinct MI300-series #AI products. And while adoption is growing, the current generation of the technology is constrained by limitations on die sizes and interconnection pitches. Thanks again to Anton Shilov and AnandTech for the full article with more background and insights via the link below 🙏💡👇 https://lnkd.in/ePCq3din #semiconductorindustry #semiconductors #semiconductor #technology #tech #it #chip #chips #ic #innovation #taiwan #foundry #nvidivia #hbm

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Studying single crystal lanthanide complexes with optical microspectroscopy https://lnkd.in/gxQ6FFKc #microscopy #spectroscopy #nuclearenergy

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Key Technologies To Extend #EUV To 14 #Angstroms 💡 Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions. The top three #foundries plan to implement high-NA EUV #lithography as early as 2025 for the 18 angstrom generation, but the replacement of single exposure high-NA (0.55) over double patterning with standard EUV (NA = 0.33) depends on whether it provides better results at a reasonable cost per #wafer. So far, 2024 has been a banner year for high-numerical aperture EUV lithography. Intel Corporation #Foundry has taken delivery of a high-NA EUV scanner. And efforts are underway at #Intel, imec, ASML, IBM, and soon at TSMC, to shore up the resist stack, EUV mask #technology, and first processes for the new scanner. The industry also received breakthrough news at SPIE in February, when imec announced it resolved 16nm lines and spaces using chemically amplified resist, and 10nm features using metal oxide resist and high-NA patterning. At Semicon West and imec’s technology forum this month, lithography experts from IBM, imec, Lam Research, and TEL gathered to share the progress and productivity advancements underway for high-NA EUV. From these and other inputs, it seems likely that EUV fabs are poised to adopt metal oxide resist stacks, new stochastic reduction strategies, angular etches, and possibly curvilinear masks to transition from the 2nm device node (22nm pitch) to the 10A node (18nm pitch, 9nm CD) for future large #AI #SoC and accelerator #chips. #DRAM makers are expected to adopt high-NA EUV in the 10A node range. Thanks again to Laura Peters and Semiconductor Engineering for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/dBqa8BE6 #semiconductors #semiconductor #semiconductormanufacturing #tech #it #innovation #geopolitics #sanctions #memory #chip #chips #icdesign

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🌟 Positive Progress for TSMC's Arizona Fab! 🌟 Exciting news from Bloomberg: TSMC’s first U.S. fab in Arizona is showing promising results! Production yields from their 4nm process are reportedly on par with those from their Taiwan facility. 🔹 Key Updates: 🌍 TSMC’s Arizona fab began producing engineering wafers in April. 🏭 The first fab aims for mass production in early 2025. 🔬 Future fabs will use cutting-edge 2nm technology to meet rising AI demand. With a $6.6 billion subsidy from the U.S. government and a total investment of $65 billion, TSMC is set to bring world-class manufacturing quality to Arizona. 🔗👀 Read more from TrendForce Corporation: https://lnkd.in/gT78JBQs 🔗👀 Read more from Bloomberg (paywall): https://lnkd.in/g85_MiUD #TSMC #Semiconductors #ArizonaFab #TechNews #Innovation #AMD

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TNL-EpiGrow simulator: Example MBE epitaxy of group IV, IV-IV, III-V, II-VI etc. HgCdTe (MCT) Epitaxial MBE Growth Solution, published in Journal of Electronic Materials . TNL-EpiGrow simulator will surely help to diagnose the formation of various defects, strain etc. The solution to obtain the crystalline MCT film USER can do optimization of MBE process input parameters through simulation. Hit & trail with different substrate options to reduce the cost associated with MCT epitaxy. For more details: https://rdcu.be/dFtco #MBE, #MOVPE, #MOCVD, #MCT, #Narrowbandgap, #Defects, #thinfilm, #Roughness, #LatticeParameter, #Epitaxy, #Growth, #ThinFilm, #HgCdTe, #Infrared, #Detector, #CdTe, #Si, #GaSb, #GaAs, #QuantumWell, #Nanosheet, #Optoelectronics, #Qualcomm, #Huawei, #IMEC, #IBM, #Intel, #Samsung, #WinSemiconductor, #TSMC, #GF, #TEL, #Wafer, #EpiWafer, #Vacancies, #dislocation, #TDD, #Crystalline, #Reactor, #GrowthRate, #Silvaco, #Synopsis, #EPIR, #Teledyne, #NASA, #DARPA, #CEALETI, #IME, #IMRI, #IHPC, #EPIR, #DRDO, #ISRO, #Defence, #NightVision, #Thermal, #Imaging, #IR, #MWIR, #LWIR, #SWIR, #T2SL, #HOT, #SMIC, #IIT, #IISC, #Teledyne, #E2V, #DRS, #LEONARDO, #ShivananthanLab, #IllinoisUniversity, #Meity, #PMO

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As modern chip designs heavily rely on SRAM, its density plays a critical role in the scaling of advanced nodes. According to the ISSCC 2025 Advance Program, the SRAM density of Intel Corporation's 18A (1.8nm-class) process aligns more closely with TSMC’s N3 than its N2 (2nm-class) process. ◾ Key Metrics: ▪️ Intel 18A: SRAM bit cell size of 0.021 µm², achieving ~31.8 Mb/mm². ▪️ TSMC N2: SRAM bit cell size of 0.0175 µm², achieving ~38 Mb/mm². ▪️ Comparison: Intel’s 18A SRAM density marks a notable improvement over Intel 4 (0.024 µm²) but doesn’t match TSMC’s aggressive N2 scaling. ◾ Notable Features: ▪️ Both nodes incorporate gate-all-around (GAA) transistors, yet TSMC has aggressively reduced SRAM sizes compared to its FinFET-based predecessors. ▪️ Intel 18A introduces a backside power delivery network (BSPDN), enhancing power efficiency and logic density potential. ◾ Bigger Picture: While SRAM density is vital, logic density often has a greater impact on overall scaling and performance. However, comparative logic density data for Intel 18A and TSMC N2 remain undisclosed. As SRAM scaling becomes increasingly challenging due to design complexities and variability at smaller nodes, the focus shifts toward balancing SRAM density, power consumption, and logic performance. What’s your take on the SRAM vs. logic density debate in advanced process technologies? Thanks again to Tom's Hardware for the full article with more background and insights click the source link in the comments below. #Semiconductors #Intel18A #TSMCN2 #SRAMDensity #ProcessTechnology #AdvancedNodes #ChipDesign #TechInnovation

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Wrapping up #DAC61, I am curious about the decision to rebrand the event as "DAC, The Chips to Systems Conference," instead of the traditional "Design Automation Conference." This is not just a simple change of words — consider the keynote speakers. Last year, they were all #EDA luminaries:  Mike Ellow (recently appointed CEO of Siemens EDA), Lip-Bu Tan (former Cadence CEO), Alberto Sangiovanni-Vincentelli (founder of both Cadence and Synopsys) and Walden C. ( Wally ) Rhines - long time CEO of Mentor Graphics. In contrast, this year, the keynote speakers were Jim Keller (Tenstorrent), Gary Patton (Intel) and Alan Lee (ADI) - all "Chip to Systems" executives. Is this a coincidence? Does it reflect EDA companies taking a lesser role at DAC? Siemens EDA (Siemens Digital Industries Software) was a notable exception as a Diamond sponsor, investing in a sizable booth and team, and hosting guests for a Giants' game at Oracle Park. (The famous Denali party is long gone...) Or is it because part of Design Automation is increasingly being done within "Chips to Systems" companies? Just look at Jim Keller discussing the importance of #opensource and Alan Lee explaining that "Product Design is Complex." What do you think? #Designautomation #chipdesign

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TSMC's Arizona facility has achieved production yields comparable to its established plants in Taiwan, indicating strong progress in its U.S. operations. The trial production at the Arizona plant uses advanced 4-nanometer process technology, essential for maximizing chip performance and efficiency. Despite a delay in full production until 2025 due to skilled labor shortages, the U.S. government plans to support TSMC with $6.6 billion in grants and up to $5 billion in loans to enhance domestic semiconductor manufacturing. #TSMC #4nm #TSMCArizona #semiconductor #semiconductors #technology #ChipsAct #chip #yield #semiconductormanufacturing Read more https://lnkd.in/dcyNGDyd

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