Meghna Baid

On Day 45 of my 100 Days of RTL Coding, I focused on converting an SR flip-flop into a T flip-flop using Verilog. This conversion required reconfiguring the logic to achieve the toggling functionality of the T flip-flop while ensuring the Set and Reset inputs were appropriately utilized. Through this process, I deepened my understanding of flip-flop functionality and the relationships between different types of sequential circuits. Looking forward to more challenges and learning ahead! #RTL #Verilog #DigitalDesign #FlipFlop #100DaysOfRTL #Day45 Here's my GitHub link : https://lnkd.in/gTfwFrhw 

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To my friends in India who are asking where they can get a copy of “Next Level Testbenches: Design Patterns in SystemVerilog and UVM:” My understanding is that KDP (Kindle Direct Publishing, the publishing arm of Amazon) does not have a print on demand plant in India. Instead, Amazon India buys books from distributors in the US and the UK and resells them in India. However, they only buy paperback books, not hardcover books. So, I put together a paperback edition with identical content as the hardcover edition. The paperback edition launched this week on Amazon with “extended distribution,” which gives permission to be sold through international distributors. I don’t know when it will reach the Indian market. The KDP website says it could take up to eight weeks to get through the distribution network. In the meantime, it’s available on amazon.com, amazon.uk, and other European markets. I’m still learning how the international publishing market works. Thank you for your patience. P.S. Ebooks were not in my original plans. There are some challenges converting a book formatted for print into an ebook. I’ll look into it, but cannot promise an ebook edition will be available.

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Hello Linkedin Fam, Rivos Inc. India (Bengaluru) is looking to hire experienced professionals in #Ethernet #PCIe #PCIExpress #PCI #Accelerator #Fabric #CPU #FloatingPoint #Debug #Trace #Cache #DDR #DFI #MemoryController #DesignVerification #DV. If this is something which interests you; please ping with updated resumes. #3+ years ~ 14 years Apart from Design Verification; there are vacancies for experienced professionals in #PhysicalDesign #CPU #SOC #PDV #PhysicalVerification #EMIR #SRAM #MemoryDesign #DFT #DesignForTest #Emulation #AcceleratorVerification #NOC Please like, share and help pass on the information to reach wider audience. Thank you all :) 😊 #jobopening #techjobs #engineeringcareers #RISC-V #accelerator #software #firmware #server #startuphiring

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🚨 Calling all Graduates! NVIDIA released its New Grad ASIC Verification Engineer role. Here's what you need to know: ⚙ Located in Santa Clara, CA ⚙ Full-time pay is ~$92,000-$180,000/yr ⚙ Full-time(40hrs/week) So if you have And have experience in SystemVerilog, C and/or C++, Python and/or Perl Then consider applying to NVIDIA now! Here's the link 👇 https://lnkd.in/gK7MNtDW You got this! ＿＿ Found this useful? Consider re-sharing 🔁 and following me Mark Benliyan for more content like this! #newgrad #nvidia #coding #softwareengineering

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Excited to share that last week I had the opportunity to present a collaborative paper between Meta and Synopsys Inc., titled "Breaking the Formal Convergence Barriers of a Floating-Point Dot-Product Block for AI/ML Accelerators," at the 61st Design Automation Conference (DAC, The Chips to Systems Conference). Additionally, it was great to catch up with exceptional individuals from academia, industry, various vendors, and startups. Achieving 100% convergence in formal verification ensures that no further bugs will be encountered, eliminating costly ECOs and potentially saving hundreds of millions in the worst-case scenario of a faulty chip (FDIV!). However, what if design complexity and C vs. RTL structural mismatches hinder formal convergence for the most complex computing block of an AI/ML accelerator? We tackled this critical challenge by employing advanced formal verification techniques and developing a methodology that breaks down convergence barriers of a multi-input and multi-precision dot product block, enabling us to achieve convergence in just a few minutes. I am honored to have collaborated with excellent co-authors from our team at Meta (Adrian Lewis, Sai Ma, Rohan Mallya, Eda Sahin) and Synopsys (Neelabja Dutta, Ashish Kapoor, Reily Jacoby). On another note, we are actively #hiring for several roles across the stack. Read more about the next-generation Meta Training and Inference Accelerator (MTIA): https://lnkd.in/gZxUvi97 #61DAC #AI #ML #Compute #Hardware #Accelerators #Verification #FormalVerification #VCFormal #hiring #Meta #Synopsys

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NVIDIA is seeking best-in-class ASIC Verification Engineer to verify the world’s leading GPUs. In this role, you will be doing unit level verification of the process scheduling and system interface hardware of the GPU. This position will be working across many #NVIDIA teams from software, to architecture, design, methodology, and more. The GPU is used in applications from consumer graphics, through self-driving cars, to artificial intelligence, all of which you will be involved in and learn about. #electricalengineering #computerengineering #computerarchitecture #asic #verification #systemverilog #testbench #debugging #uvm

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🚀 Excited to Share My 40th YouTube #techshort! 🚀 In this tech short, explore how to write a constraint in SystemVerilog to generate an array where elements form a perfect mirror pattern. Learn this fascinating technique to enhance your constraint-writing skills! 🔔 Don't forget to like, share, and subscribe for more tech shorts! #vlsi #verification #semiconductors #verilog #systemverilog #asic #designverification #interviewpreparation #constraints #uvm #podcastwithnavneet #navneettechshorts #navneettechquiz #staytuned📚

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I recently finished teaching EECS 573 "Advanced Topics in Computer Architecture", along with my teaching assistant Biniyam Tiruye, at Computer Science and Engineering at the University of Michigan. This is a graduate-level computer architecture class with new bleeding-edge content every year. This time out, we focused on the topics of i) reliable architectures (with special focus on intermittent computing, datacenter SDCs, and timing speculation), ii) secure and correct computing (with special focus on hardware security attacks, defenses, and privacy-enhanced architectures), and iii) accelerated design (with special focus on AI accelerators and beyond-AI accelerators). I always find that deep-diving into the last few years of papers on a specific computer architecture topics with students to be an enriching experience, one that often generates a lot of new ideas on how to pursue emerging challenges. I intend to post some of these thoughts here in the near future... In case you are interested in learning more about these subjects, we've made the class lecture slides publicly available here: https://lnkd.in/dfpuFqDJ #computerarchitecture #research #universityofmichigan #goblue

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📢 U.S. firm Allegro MicroSystems opens R&D centre in #Hyderabad, to #hire 400 🔥 💡 🔹️Nearly 100 highly skilled professionals have been onboarded and there are plans to scale the headcount to 500 in near future 🔹️ ▪️ #Magnetic #sensing and #power #IC solutions provider Allegro MicroSystems of the U.S. has opened a research and development centre in Hyderabad. ▪️ Nearly 100 highly #skilled #professionals have been #onboarded and there are plans to scale the #headcount to 500 in near future. The facility will be instrumental in #developing #cutting-#edge solutions for e-mobility, clean energy and automation. Setting up of the centre underscores Allegro MicroSystems commitment to advancing #India’s #semiconductor vision and highlights #Telangana’s strategic role in building a resilient, world-class semiconductor ecosystem, Industries and IT Minister D.Sridhar Babu’s office said on the R&D centre opening and the company’s senior leadership meeting him at the Secretariat on Friday (November 15, 2024). ▪️ The R&D facility will be a centre of excellence in #analog and #mixed-#signal #design, #verification and #validation for the #EV, #automotive and #robotic automation markets, driving advanced technological development and positioning Hyderabad as a leader in emerging technology solutions. Allegro MicroSystems’s decision to expand operations in Hyderabad aligns with the city’s robust infrastructure, skilled talent pool and supportive government initiatives. The company’s plans to grow headcount in Hyderabad will create significant job opportunities for skilled professionals, it said. ▪️ The setting up of the centre is a “significant step forward in our global product innovation strategy. Hyderabad’s exceptional talent pool, supportive government policies and strategic location make it an ideal hub for Allegro MicroSystems’s expansion,” CEO Vineet Nargolwala said. ▪️ India is on the verge of a semiconductor revolution and the shift towards electric vehicles is set to drive semiconductor demand since #EVs require significantly more chips than traditional vehicles. India, however, imports over 90% of its semiconductors, the Minister said. Electronics Sector Skills Council Of India (ESSCI) | I) | Electronics India For You | India Electronics and Semiconductor Association | FICCI | India Semiconductor Mission | Semiconductor Nation - Campus Connect | Semicon India | SEMI India | Semiconductor and Electronics | StatsMarketResearch | IETE IETE IETE BIT Mesra, R | hi | IETE | November 15, 2024 | #HYDERABAD | The Hindu Bureau | #AllegroMicroSystems | #chip | #US | #semiconductor | #fabrication | #Jobs | #Business | #market | #technology | #RnD | #RandD | #Semiconductors | #Wafer | thehindu.com #Details— https://lnkd.in/g25E-ia5

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🚀 Excited to Share My 16th YouTube #techshort! 🚀 Are you curious about how to create a Singleton class in SystemVerilog? Check out my latest tech short where I walk you through the steps to ensure that only one object of a class is created. 🔔 Don't forget to like, share, and subscribe for more tech shorts! #vlsi #verification #semiconductors #verilog #systemverilog #asic #designverification #interviewpreparation #constraints #uvm #podcastwithnavneet #navneettechshorts #staytuned 📚

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I come across multiple folks every year who want to switch job profile. It becomes difficult to switch after 2 years if person is not ready to relocate and compromise with salary. This is one of the reasons I recommend students to try embedded software career path first. I have conducted several surveys in LinkedIn for awareness purpose. Learning firmware or embedded software will definitely add value to PCB design background folks. Experienced folks can explore management role after firmware development skills. We have many hardware background folks in our Developer kit community. They got better opportunities after learning firmware programming. Our Ultra kit (Six months live session) can definitely help such folks due to several features: a: Learn C in various levels starting from Level 1. It depends on various types of C used in embedded software development. It includes logic building and project based hands-on approach. We have enough testimonials of C skills improvement in both students and working professionals. b: With longer duration, we can provide learning material for various architectures, RTOS, Linux and testing as well. c: PCB design background folks can try to design complete product. We have provision for this as well based on my past experience. Answer : This is possible but the complete switch over to embedded software will take some time. There are several factors : 1: If you are from an ECE background, you might have studied Microprocessor and Digital Electronics. If not, you have to study these two first. 2: You have to work on your C skills and learn firmware development with ARM based MCU. 3: If your current CTC is above 14 LPA , you have to first try to find firmware development in your organization. 4: You may also explore the team lead kind of role where you get some opportunity to work in firmware development.. 5: RTOS and Linux Application development can add value to your profile. 6: You have to be flexible for relocation. 7: Learning firmware development will definitely add value to your profile even if you don't get an immediate opportunity to switch. Answer to I have been working as PCB's design engineer for the past 7 years. I would like to switch over to the embedded software field. Is it possible? by Sanjay Kumar https://lnkd.in/gWtyirVq #embedded #opentowork #pcbdesign #embedkari

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In my first job at Qualcomm, I was part of a ~30 person team where I was the only non Indian/Pakistani. And I loved it! You would think it would create a weird dynamic. That I would feel isolated, wouldn't fully integrate, and have little in common with my desi colleagues. But that couldn't be further from the truth. I was welcomed with open arms, and I fully embraced it 👇 We ate tons of Indian food and had chai breaks. (I loved chicken vindaloo & mango lassi) We watched Bollywood movies during bring-up days. (My favorite was Singham & Robo) I started inadvertently doing the head wobble. I learned all about cricket and we played TT. I was invited to weddings in India. I picked up some Hindi phrases. I was even referred to as Alex bhai! It often times felt like I was truly in India. So I look back very fondly on those first 7 years of my career. It was such a warm and welcoming environment for a fresh graduate. I made so many wonderful friends & memories. We could have easily chosen tribalism, and kept to our own "kind". But instead, we chose unity. We celebrated our differences, not used them as a way to create separation. In times like these, where it's so easy to get caught up in the "us vs. them" narrative, it's important to remember that there is much more that unites us than divides us. So tune out the noise which commands you to hate. Choose togetherness. Choose courage. Choose love 💙

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Qualcomm vs Arm Qualcomm's central processors are properly licensed under an agreement with Arm Holdings jury found. Arm's (O9Ty.F), shares were down 1.8% in extended trading after the news, and Qualcomm's (QCOM.O), shares were up 1.8% #Qualcomm #Arm #chip #licence #Nuvia

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🚀 Excited to Share My 13th YouTube #techshort! 🚀 In this tech short, learn how to write a constraint to randomly generate 0, 1, x, and z states in SystemVerilog. Perfect for anyone looking to enhance their design verification skills and understanding of constraints in SystemVerilog. 🔔 Don't forget to like, share, and subscribe for more tech shorts! #vlsi #verification #semiconductors #verilog #systemverilog #asic #designverification #interviewpreparation #constraints #uvm #podcastwithnavneet #navneettechshorts #staytuned 📚

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🕰 Exciting News: Introducing the Clock Alarm Project Report! 🎉 I'm thrilled to announce the release of the Clock Alarm Project Report, a collaborative effort between Abhiraj Ghose and Pallav Sharma(me), under the guidance of Dr. Ashutosh Srivastava, showcasing our innovative Verilog-based Clock Alarm system developed using Verilog and Vivado Simulator! 🌟 *Project Overview:* The Clock Alarm project is a versatile system that allows users to set alarms, stopwatches, and more, all implemented using Verilog and Vivado. With features like setting a time for the alarm, stopping the alarm, and functioning like a stopwatch, our project offers a user-friendly and practical solution for time management. 🔍 *Key Features:* - Set Alarm Time: Users can easily set the desired time for the alarm to ring. - Alarm Functionality: Once the set time is reached, the alarm rings to alert the user. - Stop Alarm: Users can stop the alarm manually once it starts ringing. - Stopwatch Mode: The system also functions as a stopwatch, allowing users to track time intervals as needed. 🛠 *Tools Used:* Our project was developed using Verilog, a hardware description language, and Vivado, a comprehensive design suite provided by Xilinx. 🚀 *Next Steps:* Excited to share our findings and insights from this project with the community! Stay tuned for more updates and future projects as we continue to explore new opportunities and innovations in hardware design. 🙏 *Gratitude:* A special thank you to Bennett University, School of CSET Bennett University, India, Prof. (Dr. ) Abhay Bansal, Dr. Ashutosh Srivastava and everyone who has supported us throughout this project, including mentors and peers. Your encouragement and guidance have been invaluable to our success. Let's continue pushing the boundaries of innovation together! ⏰💡 #ClockAlarm #Verilog #Vivado #HardwareDesign #ProjectReport #Innovation

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