Smaran Sinha

AXI is a multi channel bus which is popularly used as an interfacing protocol between multiple IP's and is useful both in RTL design and ASIC Verification. Below are the key concepts which are needed to understand AXI protocol in depth. [1] Difference between AXI and AHB. Number of Channels used in AXI. Why there is no separate Read response on AXI. [2] What are out of order and outstanding transaction in AXI. [3] What is the address boundary that slave can access in AXI. [4] Transfer mechanism for Write / Read with / without delay. [5] Valid and Ready hand shaking mechanism. What is deadlock condition. How to overcome it. [6] Difference b/w Incrementing and Wrapping Burst. What is a Fixed Burst type. [7] Difference b/w Bufferable and Cacheable type of transaction in AXI. [8] Complete understanding of Exclusive access phenomenon. Difference b/w OKAY and EXOKAY response. [9] What is a Locked access in AXI3. Why it is removed in AXI4. [10] What are the conditions for SLVERR and DECERR. [11] What is a QOS support for AXI4. What are the significance of AxREGION and AxUSER in AXI4. [12] Difference b/w AXI3 and AXI4. [13] What is a write interleaving method in AXI3 and why it's removed in AXI4. #vlsi #asic #semiconductorindustry #electricalengineering

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🚨 **Ensuring Proper PG Bias Off State in IC Designs Using Synopsys VSLP Tool** 🚨 In Integrated Circuit (IC) design, managing power gating bias off states correctly is crucial for optimizing power efficiency and ensuring reliable operation. The Synopsys VSLP tool is essential for detecting and resolving pg_biasoff_state issues. Here’s a concise overview of what pg_biasoff_state entails and its importance. ### **What is PG Bias Off State?** **PG Bias Off State** refers to the condition where biasing of power-gated domains is correctly turned off to save power. Ensuring this state is properly managed is vital for achieving power efficiency and maintaining functional integrity. ### **Importance of Addressing PG Bias Off State Violations** - **Power Efficiency**: Proper management of bias off states reduces power consumption, enhancing the overall energy efficiency of the IC. - **Functional Integrity**: Correctly handling bias off states ensures that power-gated domains are fully powered down without unintended leakage or partial functionality. - **Reliability**: Ensuring proper bias off states enhances the reliability and stability of the IC, preventing potential issues from partial biasing. - **Thermal Management**: Reducing power consumption through effective bias off state management helps in thermal management by lowering heat generation. ### **Detecting and Addressing PG Bias Off State Violations with Synopsys VSLP** The Synopsys VSLP tool provides advanced capabilities to detect and rectify issues related to PG bias off states, ensuring robust and reliable IC designs. #### **1. Static Analysis** - **Bias Off State Checks**: Analyze the design to ensure that power-gated domains are correctly biased off when required. - **State Transition Verification**: Verify that transitions to and from the bias off state are managed correctly, preventing unintended power leakage. #### **2. Dynamic Simulation** - **Power Down Scenarios**: Simulate various power down scenarios to assess the impact on system functionality and ensure proper bias off state management. - **Power Consumption Analysis**: Monitor power consumption during bias off states to identify any irregularities or inefficiencies. ### **Best Practices for Managing PG Bias Off States** 1. **Clear Power Management Strategy**: Develop a clear strategy for managing bias off states, including guidelines for when and how components should enter and exit these states. 2. **Continuous Validation**: Regularly validate bias off state implementation throughout the design process to catch and address issues early. 3. **Collaborative Approach**: Work closely with power management and system design teams to ensure that bias off states are integrated seamlessly into the overall design. 4. **Advanced Tool Utilization**: Use advanced tools like Synopsys VSLP for automated detection and correction of bias off state issues. #workwithuppula #synopsys #VSLPTool #powerefficiency Thanks, Vishnu

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Recently, Apple has launched the iPhone 16 series, enabling WiFi 7 for iPhone users. Let us do some brief system-level calculations to understand noise and ADC requirements.   Assumptions: Modulation Scheme: 4096-QAM Channel Bandwidth: 320 MHz Received Power (P_RX): -50 dBm Front-end RX Gain ( G ): 25 dB Front-end Noise Figure ( NF ): 10 dB Thermal Noise Power Density ( N_0 ): -174 dBm/Hz Step 1: Thermal Noise Power Calculation The noise power density is a function of thermal noise at room temperature (290K). Given the bandwidth B = 320 MHz, the total noise power over the bandwidth is: N_total = N_0 + 10log10(B) N_total = -174 + 85.05 = -88.95 dBm Step 2: Adjust for Noise Figure by Front End The receiver’s noise figure (NF) adds noise to the system. Adjust the total noise power by the noise figure: N_output = N_total + NF N_output = -88.95 dBm + 10 dB = -78.95 dBm This represents the total noise power at the output of the front end. Step 3: Signal Power at the ADC Input The signal power at the input of the ADC is the received power amplified by the front-end gain (G = 25 dB). P_ADC_in = -50 dBm + 25 dB = -25 dBm Step 4: Signal-to-Noise Ratio (SNR) Calculation The SNR at the ADC is the difference between the signal power at the ADC input and the total noise power at the output: SNR = P_ADC_in – N_output SNR = -25 dBm - (-78.95 dBm) = 53.95 dB This is the SNR at the input of the ADC. Step 5: Determine the ADC Resolution (ENOB) The effective number of bits (ENOB) of the ADC can be determined from the SNR using the relation: SNR = 6.02 x ENOB + 1.76 dB ENOB = (SNR - 1.76) / 6.02 ENOB = (53.95 - 1.76) / 6.02 = 8.67 bits Step 6: Verify SNR Requirement for 4096-QAM For 4096-QAM, the required SNR can be approximated by: SNR_required = 10log10(M), where M = 4096 for 4096-QAM SNR_required = 10log10(4096) = 36 dB Since the calculated SNR at the ADC input (53.95 dB) exceeds the required SNR for 4096-QAM (36 dB), the system is well within the acceptable range for decoding the signal. Step 7: ADC Full-Scale Dynamic Range To ensure proper ADC operation, the full-scale range of the ADC should encompass both the noise floor and the signal power. The total noise power at the ADC input: N_output = -78.95 dBm The signal power at the ADC input: P_ADC_in = -25 dBm Thus, the required dynamic range (difference between the signal and noise) is: Dynamic Range = P_ADC_in – N_output = -25 - (-78.95) = 53.95 dB The ENOB of 8.67 bits corresponds to a dynamic range DR = 6.02 x 8.67 = 52.2 dB This is close to the 53.95 dB SNR at the input of the ADC. Conclusion: For a typical WiFi 7 system with 4096-QAM and 320 MHz bandwidth: Required ADC ENOB: 8.67 bits. However, a nominal ADC resolution of 10 bits would provide adequate performance with design margins for implementation losses, ensuring the system can properly digitize the incoming signal. *Please note that Front End gain is a variable that also plays a crucial role in properly functioning WiFi Receiver.

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Just a thought RTL Design has few logics which is not required as per the design specifications, this portion of code gets excluded in code coverage analysis. By knowing this fact we still synthesis the logic and it increases the gate counts. but functionaly this logic has no use. Now can this be a area for AI based tool to discard that portion of logic during synthesis and we reduce the gate count?

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© Topic: VLSI Glossary © ⏭ ⏭⏭ ⏭ GrowVLSI ⏮ ⏮ ⏮ ⏮ (A-S posted few days back) T: TB- Tera Byte TN- Technology Node TG- Transmission Gate TTL- Transistor Transistor Logic TT- Typical Typical (TT is the corner where both NMOS and PMOS are typical, when this corner is enabled the processing parameters may be typical/hard because corner analysis does include all the process variation possiblities ) TCL- Tool Command Language TF- Technology File 😍It is an ASCII file in which information about all the metal layers, vias and their design rules are available😍 TLU+: Timing Library Update/Table LookUp 😍 TLU+ file provides RC parasitic information of metal per unit length which is used to calculate the net delay. All TLU+ file data is completely technology dependent and is given by Foundry 😍 TNS- Total Negative Slack U: ULVT- Ultra Low Threshold Voltage UPF- Unified Power Format ULSI- Ultra Large Scale Integration V: VLSI- Very Large Scale Integration VHDL- VHSIC(Very High Speed Integrated Circuit) Hardware Descriptive Language W: WNS- Worst Negative Slack X, Y, Z: Didnot find anything Content Writer B. Lokeshwar

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Hello Linkedin Fam, Rivos Inc. India (Bengaluru) is looking to hire experienced professionals in #Ethernet #PCIe #PCIExpress #PCI #Accelerator #Fabric #CPU #FloatingPoint #Debug #Trace #Cache #DDR #DFI #MemoryController #DesignVerification #DV. If this is something which interests you; please ping with updated resumes. #3+ years ~ 14 years Apart from Design Verification; there are vacancies for experienced professionals in #PhysicalDesign #CPU #SOC #PDV #PhysicalVerification #EMIR #SRAM #MemoryDesign #DFT #DesignForTest #Emulation #AcceleratorVerification #NOC Please like, share and help pass on the information to reach wider audience. Thank you all :) 😊 #jobopening #techjobs #engineeringcareers #RISC-V #accelerator #software #firmware #server #startuphiring

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Hello Connections Click on the below link to understand PCIe Config Space and visit the channel to see other videos related to PCIe protocol. Subscribe to my YouTube channel for more such informative videos. https://lnkd.in/grYJmusS

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🚨 **Addressing UPF Supply Undriven Violations in IC Designs Using Synopsys VSLP Tool** 🚨 In Integrated Circuit (IC) design, maintaining robust power management is critical. A key aspect is ensuring that all power supply nets defined in the Unified Power Format (UPF) are properly driven. The Synopsys VSLP tool is essential for identifying and resolving UPF supply undriven violations. Here’s a concise overview of what this entails and its importance. ### **What is UPF Supply Undriven?** **UPF Supply Undriven** refers to instances where supply nets specified in the UPF are not connected to any driving source, leading to potential functional and power management issues. ### **Significance of Resolving UPF Supply Undriven Violations** - **Functional Integrity**: Undriven supply nets can cause parts of the IC to malfunction due to lack of proper voltage, leading to errors. - **Power Efficiency**: Ensuring all supply nets are driven helps optimize power distribution, reducing power wastage. - **Reliability**: Properly driven supply nets minimize the risk of voltage drops and instability, enhancing the IC’s reliability. - **Compliance**: Ensuring all UPF-defined nets are driven is essential for meeting industry standards and ensuring design robustness. ### **Detecting and Resolving UPF Supply Undriven Violations with Synopsys VSLP** The Synopsys VSLP tool provides comprehensive capabilities to detect and address UPF supply undriven violations, ensuring robust and reliable IC designs. #### **1. Static Analysis** - **Supply Net Checks**: The tool scans the design to identify undriven supply nets defined in the UPF. - **Connectivity Verification**: Ensures all power supply nets are properly connected to driving sources. #### **2. Dynamic Verification** - **Power Scenario Simulation**: Simulate different operating conditions to confirm all supply nets are driven as required. - **Dynamic Power Analysis**: Analyze power distribution to identify and rectify undriven supply nets. #### **3. Rule Checking and Reporting** - **Design Rule Checks (DRC)**: Automatically enforce rules related to power supply connections, flagging undriven nets. - **Detailed Reporting**: Generate comprehensive reports outlining undriven supply nets and providing recommendations for correction. ### **Best Practices for Ensuring Driven UPF Supply Nets** 1. **Clear Power Specifications**: Define and adhere to clear power supply specifications for all UPF nets. 2. **Continuous Verification**: Regularly verify supply net connectivity throughout the design process to catch issues early. 3. **Collaborative Approach**: Work closely with design and verification teams to ensure all power nets are properly driven. 4. **Advanced Tool Utilization**: Utilize tools like Synopsys VSLP for automated detection and correction of undriven supply nets. #semiconductors #workwithuppula Thank, Vishnu

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Dear Chip Designers, . . . In the fast faced Semiconductor Industry, A Strong Individuals can Resolve Perceived Weaknesses in Teams. A New hire team lead can make or break the entire team, I have seen this multiple times. In the dynamic landscape of the Semiconductor industry, success often hinges on the collective strength of teams. However, even the most skilled teams may face challenges when dealing with perceived weaknesses among members. In this, lets delve into the transformative power of strong individuals in resolving these issues, ultimately fostering a culture of collaboration, innovation, and success. Identifying Perceived Weaknesses: Before delving into solutions, it's crucial to identify the perceived weaknesses that may hinder team performance. These can range from lack of technical proficiency to communication barriers or even interpersonal conflicts. The Role of Strong Individuals: Strong individuals possess a unique set of qualities that can significantly impact team dynamics. These individuals are not only technically proficient but also exhibit strong leadership, communication, and problem-solving skills. Their presence within teams can serve as a catalyst for positive change, bridging gaps and inspiring others to elevate their performance. Key Solutions and Strategies: Lead by Example: Strong individuals lead not only through their words but also through their actions. By setting high standards and demonstrating commitment to excellence, they inspire others to follow suit. Facilitate Open Communication: Effective communication is the cornerstone of successful teams. Strong individuals actively foster an environment where team members feel comfortable expressing their ideas, concerns, and feedback. Offer Mentorship and Support: Strong individuals recognize the importance of nurturing talent within the team. They willingly share their knowledge and experiences, empowering others to grow and develop their skills. Address Conflict Constructively: Conflict is inevitable within any team, but strong individuals approach it as an opportunity for growth rather than a hindrance. They facilitate constructive discussions and work towards finding mutually beneficial solutions. Celebrate Diversity: Strong individuals appreciate the value of diversity in perspectives and backgrounds. They actively seek out input from all team members, recognizing that innovation thrives in an inclusive environment. Case Studies and Success Stories: To illustrate the effectiveness of leveraging strong individuals within teams, we present real-life case studies from leading semiconductor companies. These stories highlight how the presence of strong individuals has transformed teams, overcoming challenges and achieving remarkable results. As we move forward, let us recognize and empower these individuals to drive positive change and propel our industry towards new heights. #semiconductor #Semiconductors #Chip #VLSI

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Class B amplifiers are sometimes OK for RF but not audio. Why? 👇🏽 Class B amplifiers provide a highly distorted output signal, but with good amplification efficiency. For many RF applications, it is okay to distort the carrier signal as long as the modulation is not affected. The baseband information can still be retrieved. Class B won't work for audio. It is a complex time-varying signal which needs to be accurately amplified. To still get Class B efficiencies, the push-pull amplifier was invented. It is a differential version of a Class B amplifier that can produce amplification with good efficiency. If you'd like to learn more about Class B and push-pull amplifiers, stay tuned for this week's newsletter. ✍🏼 Sign up here: www.viksnewsletter.com What is your experience with Class B or audio? Let me know! ~~ 🔔 Follow me for posts on RF engineering ♻️ Repost if you found it useful.

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A newspaper clipping that brings back memories of Texas Instruments Educators' Conference held in 2013 at Nimhans Convention Center. The highlight of the conference was the exhibition of projects which were carried out by students across India, who had enrolled in the TI Analog Design Contest. After a modest beginning with ten institutions and 20 projects, year after year, we saw the number of submissions growing at a rate higher than Moore's law! Executing the contest was a massive effort. It included distribution of electronic components to the participants, receiving periodic updates on the progress of the projects, finding help for students who were facing difficulties, arranging the exhibition, having the contests judged and declaring the prizes in the Educators' Conference. We tried some interesting ideas in the 2013 conference. As part of the inauguration, we invited students of IISc who worked with Prof Jamadagni to enact small technoskits to bring out the innovation in the projects. Back in 2013, when IoT was still a new idea, a project was carried out by Prof Jamadagni's students, based on the idea of the Infinite Coffee Cup by Gene Frantz. This project was demo-enacted on the stage. The infinite coffee cup has built in electronics to sense when the cup is empty and signals to the waiter for a refill. The conference also had paper presentation sessions where the demoed projects were presented as papers . We brought out the conference proceedings as a book which published by Chitkara University thanks to help from Prof Rajnish Sharma. We had invited Prof Dhananjay Gadre to make a special inaugural lamp for the inauguration. Steve Lyle and Brad Ruziska from TI Dallas and Bobby Mitra and Sanjay Bhan from TI India inaugurated the conference by lighting an electronic lamp with a remote controller. Prof Gadre went on to create multiple versions of the inaugural lamp with more technology integration. My former colleagues Sagar Juneja and Vaibhav Agarwal were helping me in organising the conference. My former colleague Narahari helped in getting press coverage for the conference. I have not mentioned the names of several colleagues from TI and many University Professors who played a role in the success of the conference. #texasinstruments #education #embeddedsystems #iot #contest #conference #university

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Semiconductors are the backbone of modern technology, but have you heard about VLSI? Prepare to be amazed by the evolution of telecom industry with #TechFacts⚡️ Department of Telecommunications ( DOT ) #didyouknowfacts #facts #semiconductors #vlsi #telecom

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📢 U.S. firm Allegro MicroSystems opens R&D centre in #Hyderabad, to #hire 400 🔥 💡 🔹️Nearly 100 highly skilled professionals have been onboarded and there are plans to scale the headcount to 500 in near future 🔹️ ▪️ #Magnetic #sensing and #power #IC solutions provider Allegro MicroSystems of the U.S. has opened a research and development centre in Hyderabad. ▪️ Nearly 100 highly #skilled #professionals have been #onboarded and there are plans to scale the #headcount to 500 in near future. The facility will be instrumental in #developing #cutting-#edge solutions for e-mobility, clean energy and automation. Setting up of the centre underscores Allegro MicroSystems commitment to advancing #India’s #semiconductor vision and highlights #Telangana’s strategic role in building a resilient, world-class semiconductor ecosystem, Industries and IT Minister D.Sridhar Babu’s office said on the R&D centre opening and the company’s senior leadership meeting him at the Secretariat on Friday (November 15, 2024). ▪️ The R&D facility will be a centre of excellence in #analog and #mixed-#signal #design, #verification and #validation for the #EV, #automotive and #robotic automation markets, driving advanced technological development and positioning Hyderabad as a leader in emerging technology solutions. Allegro MicroSystems’s decision to expand operations in Hyderabad aligns with the city’s robust infrastructure, skilled talent pool and supportive government initiatives. The company’s plans to grow headcount in Hyderabad will create significant job opportunities for skilled professionals, it said. ▪️ The setting up of the centre is a “significant step forward in our global product innovation strategy. Hyderabad’s exceptional talent pool, supportive government policies and strategic location make it an ideal hub for Allegro MicroSystems’s expansion,” CEO Vineet Nargolwala said. ▪️ India is on the verge of a semiconductor revolution and the shift towards electric vehicles is set to drive semiconductor demand since #EVs require significantly more chips than traditional vehicles. India, however, imports over 90% of its semiconductors, the Minister said. Electronics Sector Skills Council Of India (ESSCI) | I) | Electronics India For You | India Electronics and Semiconductor Association | FICCI | India Semiconductor Mission | Semiconductor Nation - Campus Connect | Semicon India | SEMI India | Semiconductor and Electronics | StatsMarketResearch | IETE IETE IETE BIT Mesra, R | hi | IETE | November 15, 2024 | #HYDERABAD | The Hindu Bureau | #AllegroMicroSystems | #chip | #US | #semiconductor | #fabrication | #Jobs | #Business | #market | #technology | #RnD | #RandD | #Semiconductors | #Wafer | thehindu.com #Details— https://lnkd.in/g25E-ia5

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Mirafra Software Technology Hiring Multimedia Framework/Device Driver Leads for Hyderabad location !!! Requirement 1- Android/Linux audio lead Job Description: ● Deep understanding of the Android audio architecture, including Audio Flinger, Audio Policy Service, and Audio Track/Audio Record classes. ● Familiarity with how the Android audio framework interacts with the underlying hardware through the Audio Hardware Abstraction Layer (HAL). ● In-depth knowledge of audio frameworks such as ALSA and PulseAudio for Linux. ● Experience with Android’s audio HAL (Hardware Abstraction Layer) and AudioFlinger. ● Understanding of the Android Audio Manager and MediaCodec. ● Knowledge of standard audio protocols (e.g., I2S, SPDIF, HDMI audio). ● Understanding of audio codecs and formats (e.g., PCM, MP3, AAC). ● Expertise in developing and maintaining audio device drivers. ● Familiarity with driver frameworks and APIs used for audio hardware integration. Requirement 2 - Android/Linux camera/video lead Job Description: ● Experience working with full camera software stack - application, camera services, HAL, Camera kernel and drivers ● Understanding of Linux camera frameworks such as V4L2 (Video4Linux2) and how they manage camera hardware and video capture. ● Familiarity with the Android camera framework, including Camera HAL (Hardware Abstraction Layer), CameraService, and CameraManager. ● Expertise in developing and customizing the Camera HAL to interface between the Android camera framework and camera hardware. ● Knowledge of HAL interfaces, including how to implement and extend HAL functions for different camera modules. ● Understanding of image processing algorithms and how they are applied in the camera pipeline, such as auto-focus, white balance, and exposure control. ● Camera sensor driver development and integration into Linux/Android ecosystem Requirement 3 - Android/Linux display/graphics lead Job Description: ● In-depth knowledge of Android’s display stack, including Surface Flinger, Hardware Composer (HWC), and the various layers involved in rendering and compositing ● Deep understand of display hardware accelerator and graphics hardware rendering pipeline and respective software flows ● Experience with Android’s display manager and handling different display modes, resolutions, and refresh rates ● Experience with developing or customizing display drivers (LCD, MIPI, HDMI, LVDS) including integration with Android’s display HAL (Hardware Abstraction Layer). ● Proficiency in graphics APIs such as OpenGL ES, Vulkan, ● Experience with Linux kernel internals and writing kernel modules related to display and graphics. ● Experience with performance profiling tools and techniques for identifying and resolving graphics/display issues. Exp-10-15 years Location: Hyderabad Notice Period: Immediate Interested can share relevant resume to maheshvastrad@mirafra.com

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9th Episode is out now This Episode has 1 important Gate 2024 question on Schmitt Trigger and an Integrator circuit, including important concepts of positive and negative feedback.. If you really like my video then press the 👍 button and also subscribe to our channel to learn more concepts in the upcoming episodes , and if have any doubts do Comment.. *YOUR FEEDBACK IS IMPORTANT FOR US* https://lnkd.in/g5kvYdyK

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Important methods in Digital Design to optimize Boolean logic in VLSI: To minimise or optimise the Boolean expression of digital logic theorems and laws related to digital logic or K-map, reduction techniques should be adopted as per the need. When the number of variables are four in a sop or pos expression, k map can able to reduce them easily. Even upto five variable and maximum upto 6 variables K map can able to perform quite efficiently. For 5 variable(ABCDE), 32 combinations are possible so two blocks of 4 variable k map are built from (0 to 15) and (16 to 31) and for BCDE, A is taken for both 0 and 1. For 6 variables, 64 combinations are possible, so mapping is done on the basis of four, four variable k map. But beyond that k map technique fails to meet the demand. So here comes the tabulation method. ✓ Tabulation method: Tabulation method in digital logic is necessary to optimise the Boolean expression when the number of variables are large, to be more precise more than six. There are two approaches to this. [1] Variable Entered Mapping (VEM) : VEM is just an extension of the K map approach where a dummy variable is AND ed with each of the minterm or the maxterm of the expression for either assertion or de assertion. That particular dummy variable can be customised according to needs and can be either on and off . Instead of filling up the mappings with corresponding 1's and 0's, VEM contain function of variables. [2] Quine-McCluskey Method: This is a another tabular method and is particularly used when both K map and VEM approach fails. The concept behind Quine-McCluskey method is the combining method approach where AB(bar) + AB = A(B + B(bar)) = A. ✓ Combine all the minterm of the expression into a common group and to first find the prime implicants of the Boolean logic. ✓ Group the prime implications and from that deduce the essential prime implicants by constructing table. ✓ Further from the essential prime implicants reduce it further to another set of essential prime implicants. ✓ Remove the earlier prime implicants where it only remained with the rows and columns with maximum number of minterm and maxterm. Drawbacks of QM method: a] Prime Implicants grows very huge making the solution space quite large. b] Difficult to generate all PI. [3] Petrick's method: It eliminates the problem of QM method, by reducing or eliminating the EPI rows and columns. [4] Espresso: It produces a minimized table which is very useful for Synthesis of the digital logic. ✓ Other important methods: [1] Consensus theorem: It helps to reduce the redundant terms from the Boolean description. [2] Binary Decision Diagram (BDD): Optimises an expression by factoring into either 0/1 and then decide which path to move. [3] Flattening / Factoring: They are the method to optimise an unoptimized RTL description. #vlsi #asic #electronics #electricalengineering

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Watch :https://lnkd.in/dQn3pgPk 🌟 Introduction & Working Principle of MOSFET 🌟 The MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is one of the most crucial components in modern electronics, powering everything from microprocessors to power supplies. Its versatility and efficiency make it indispensable in the world of semiconductors. What is a MOSFET? A MOSFET is a type of transistor used to amplify or switch electronic signals. It operates by controlling the flow of current between its source and drain terminals using voltage applied to the gate terminal. Working Principle Structure: A MOSFET consists of a semiconductor substrate (typically silicon), with source, drain, and gate terminals. The gate is separated from the substrate by a thin insulating layer of silicon dioxide. How it Works: When a voltage is applied to the gate terminal, it creates an electric field that controls the flow of electrons (or holes) between the source and drain. This ability to control current flow makes the MOSFET act like a switch or amplifier. Two Main Types: N-Channel MOSFET: Conducts when a positive voltage is applied to the gate. P-Channel MOSFET: Conducts when a negative voltage is applied to the gate. Applications Digital Circuits: Logic gates, microprocessors, memory chips. Power Electronics: Voltage regulators, motor drives, inverters. Analog Circuits: Amplifiers, oscillators, and RF circuits. The MOSFET's ability to operate at high speeds and handle significant power makes it a cornerstone of modern technology. Check our Premium VLSI Courses : https://lnkd.in/g5kVruWq Join VLSI Jobs : Whatsapp Channel : https://lnkd.in/dHsz2TZh Download VLSI FOR ALL Community App : https://lnkd.in/dB_QDcHT FREE Mentorship : https://wa.me/918218599381 Call us on (+91)-9643070368 Apple Users App Link : https://lnkd.in/dA_7YmYJ Write us on info@vlsiforall.com #vlsiforall #vlsijobs #freshers #internship #vlsitraining #Semiconductor #Innovation #Technology #Beginners #Electronics #Engineering #VLSI #EmbeddedSystems #HardwareDesign #InternshipOpportunity #mosfet

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𝑾𝒉𝒚 𝑺𝑻𝑴32 𝒆𝒗𝒂𝒍𝒖𝒂𝒕𝒊𝒐𝒏 𝒃𝒐𝒂𝒓𝒅 ?  I have a range of evaluation boards from all well known semiconductor companies including NxP , ST, Nuvoton, TI , Microchip, Broadcom, Nordic, NVIDIA etc. That was part of my investment. I got loaner boards from ST, NxP and Nuvoton. I used following parameters to decide evaluation board : 1: 𝘾𝙤𝙢𝙥𝙖𝙣𝙮 𝙝𝙞𝙨𝙩𝙤𝙧𝙮 I have used ST devices around 1998 as well. 2: 𝙍𝙤𝙖𝙙𝙢𝙖𝙥 : They have a range of products in various domains 3: 𝘾𝙤𝙨𝙩: It is most important factor and their boards are available in Arduino range as well. 4: 𝙀𝙘𝙤𝙨𝙮𝙨𝙩𝙚𝙢 : They have a variety of tools for Pin multiplexing, Flash programming, Debugging and even for AI. 5: 𝙎𝙪𝙥𝙥𝙤𝙧𝙩 :  I never had issue in contacting ST Marketing , Development , FAE and distributor FAEs . In fact , now my student is also supporting ST devices in India. I was invited for a combined session with faculty as well. 6: 𝙅𝙤𝙗 𝙤𝙥𝙥𝙤𝙧𝙩𝙪𝙣𝙞𝙩𝙞𝙚𝙨 : Since STM32 is based on ARM and being widely used in India. It increases your possibility to get job. Here is outcome of my experience with ST device. This week was little bit interesting in embedded system live sessions. 1: Enabled one US based student in the STM32 evaluation board which I never used. It was done in live session. We supported multiple devices in past but it was instant support over live session. 2: Yesterday also another US based student shared board over camera. We started with default HAL project to do sanity check. First surprise was warning " Obsolete board" . We ignored and continued . Next surprise was "Insufficient flash memory" even with default configuration. This was because it had enabled all peripherals. I asked student to put while(1); in the beginning. Linker was kind enough to discard all other code and we could reach at main() at least. This was simple but important for student to move ahead. Both above students are working professionals in US and joined Embedkari for a refresh cycle. For joining Embedkari, no shubh muhurt is required because every moment is part of God's creation 😀 ... Join anytime . and #salarybadhao #microcontroller #microcontrollers #embedded #embeddedsystem #embeddedlinux #embeddedc #freertos #firmware #firmwareengineer #firmwarejobs #devicedriver #softwareengineers #electronics #embeddedjobs #embeddedsystems #embeddedengineer #embedkari #opentowork #freshers #stm32

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