Sujay Singh, PhD

Power, performance, and area/cost have been the three optimization targets for decades, but are they relevant in today’s complex systems? Semiconductor Engineering explores this topic, with comments from Expedera. https://ow.ly/HOs150Tmef5

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①TSMC: Major breakthroughs in 2nm and silicon photonics; plans to build two new wafer fabs...https://lnkd.in/g76PU36E ②Another silicon carbide (SiC) wafer factory project canceled...https://lnkd.in/gsDZ5yzt

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Each new node brings more complex design rules and device models - too much for design teams to fully leverage alone. Instead, they must align closely with foundries and EDA partners.

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Excited to lead this effort on AI for Wireless Chip Design, as one of the three anticipated awardees of the $30 million dollar inaugural proposal call from National Semiconductor Technology Center (Natcast.org), established through the US Chips and Science Act by the Biden-Harris administration. AI-enabled RFIC design started as a small effort from our group (nearly unfunded) about four years ago. Without any prior work, we went through quite a bit of sweat, tears, and failed ideas, before we demonstrated (in 2022) the first examples of how AI can discover new architectures for wireless chips, and allow rapid designs on demand. This has now evolved into a substantial effort across academia, industry and government. Expectedly, a highly multi-disciplinary effort--immensely proud of my students, who had to learn multiple areas from complex chip design to electromagnetics to AI, and build the foundations from scratch. Congrats to Emir Ali Karahan, Zheng Liu, Jonathan Zhou, and all the members of the group. Excited to partner with Hossein Hashemi, Ioannis Savidis, Xuan 'Silvia' Zhang, Mengdi Wang, Raytheon, Cadence Design Systems, and Keysight Technologies. https://lnkd.in/eZFfnyPY #AI #RFIC Princeton University, Princeton Engineering, Princeton ECE, Princeton Research

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Exploring the Fabless Semiconductor Revolution: Innovations in Chip Design Expert VLSI professor from CEERI Pilani dives deep into the world of VLSI (Very Large Scale Integration), explaining what VLSI is, how the industry is growing, and the opportunities it presents for aspiring professionals. Whether you're a student, engineer, or enthusiast looking to understand the intricacies of the semiconductor industry, this video will provide a thorough overview. watch video here https://lnkd.in/gAnxu-Fz #futurewiz #AI #semiconductor #nvidia #placement #vlsijobs #vlsi

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Exploring the Fabless Semiconductor Revolution: Innovations in Chip Design Expert VLSI professor from CEERI Pilani dives deep into the world of VLSI (Very Large Scale Integration), explaining what VLSI is, how the industry is growing, and the opportunities it presents for aspiring professionals. Whether you're a student, engineer, or enthusiast looking to understand the intricacies of the semiconductor industry, this video will provide a thorough overview. watch video here https://lnkd.in/gAnxu-Fz #futurewiz #AI #semiconductor #nvidia #placement #vlsijobs #vlsi

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Boosting U.S. Semiconductor Manufacturing: CHIPS Act Milestones Semiconductor Industry Association (SIA) has praised the finalization of CHIPS Act incentives for GlobalFoundries’ manufacturing projects in New York and Vermont, a key step in advancing U.S. semiconductor production. These incentives, coordinated by the U.S. Department of Commerce, will bolster sectors like automotive, communications, and defense, while enhancing national security and economic competitiveness. Since its enactment, the CHIPS and Science Act has catalyzed significant progress: ▪ 90 new projects announced across 28 U.S. states. ▪ Over 58,000 jobs directly in the semiconductor ecosystem, with ripple effects creating hundreds of thousands of additional jobs. ▪ Hundreds of billions of dollars in private investments. A recent SIA-Boston Consulting Group report projects U.S. domestic semiconductor manufacturing capacity will triple from 2022 to 2032—a staggering 203% increase, the largest globally. Additionally, the U.S. is expected to capture 28% of global semiconductor capital expenditures from 2024 to 2032. With momentum building, the SIA urges Washington to expedite further CHIPS agreements to sustain U.S. leadership in chip technology. How will this reshape the global semiconductor landscape? Share your thoughts below! Thanks again to Semiconductor Industry Association for the full article with more background and insights click the source link in the comments below. #Semiconductors #CHIPSAct #Manufacturing

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Tune into the Daily Semiconductor Industry Podcast for December 2nd, 2024! Hello, friends, followers, and listeners! I need your support. We pour a lot of time and effort into creating daily content for LinkedIn, and your engagement is what keeps us going. When you like, comment, and share our posts, it helps us reach a broader audience and grow this platform. Sharing truly is caring, and it allows shows like ours to connect with more industry professionals. Please take a moment to like, comment, repost, and share our content so we can continue delivering the latest updates and insights to the semiconductor community. Your support makes all the difference! ▪️Intel Corporation CEO Pat Gelsinger retires: Intel CEO Pat Gelsinger retired abruptly, with CFO David Zinsner and Michelle Johnston Holthaus named interim co-CEOs. Gelsinger's tenure was marked by aggressive restructuring, mass layoffs, and attempts to revitalize Intel's foundry business under its IDM 2.0 strategy. Despite progress in manufacturing, challenges in AI, market share, and delayed products persist. ▪️Samsung Electronics’s executive layoffs: Samsung reportedly cut over 100 senior executives from its semiconductor division, the largest in its history, sparking concerns about talent leakage to Chinese firms. China offers significantly higher salaries, raising fears of intellectual property risks. South Korea is striving to retain key talent through policy measures. ▪️EU's call for "Chips Act 2.0": SEMI Europe advocates for an expanded EU Chips Act to bolster the semiconductor ecosystem, align industrial policies, and counter US-China strategies. Recommendations include fast-track processes, supply chain incentives, and fostering foundational and green tech chips. We have some major updates in the semiconductor world, and we'd like to give a huge thank you to our sponsor,ventureLAB, for powering today’s industry review! ventureLAB is leading the way in helping startups in hardware and enterprise software thrive, playing a crucial role in advancing Canada’s semiconductor and AI ecosystems. #IntelLeadership #SemiconductorIndustry #TechLayoffs #ChipsAct #SemiconductorPolicy #TechTalent #InnovationInTech #SemiconductorEcosystem

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TSMC Advances Silicon Photonics Strategy: A Leap Towards Optical Era TSMC is making significant strides in silicon photonics, according to the Economic Daily News. Recent breakthroughs include integrating co-packaged optics (CPO) with advanced semiconductor packaging. Sample deliveries are projected for early 2025, with 1.6T optical transmission products expected in mass production by late 2025. Broadcom and NVIDIA are likely among the first customers. ◾ Key highlights include: ▪️ Successful trial production of the micro ring modulator (MRM) on TSMC's 3nm process, enabling CPO integration with HPC and AI ASIC chips. ▪️ Potential leap from electrical to optical signal transmission, addressing current limitations in speed and heat dissipation. ▪️ Challenges persist with CPO module packaging due to complexity and low yield rates, possibly leading to outsourced optical engine packaging. NVIDIA reportedly plans to adopt CPO for its GB300 chips (H2 2025) and Rubin architecture, aiming to enhance NVLink interconnect performance. These advancements position TSMC at the forefront of the optical computing era, reshaping the future of high-performance computing and AI applications. What are your thoughts on the potential impact of silicon photonics in AI and HPC? Share below! Thanks again to TrendForce Corporation for the full article with more background and insights click the source link in the comments below. #Semiconductors #SiliconPhotonics #AI #HPC #TSMC

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Ansys Government Initiatives Selected to Join Microelectronics Commons to Support National Security #ansys #government #microelectronics #security #semieda #semiconductor #semiconductors #semiconductorindustry #semiconductormanufacturing #semiwiki https://lnkd.in/g_gwVAvS

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Check out the latest technical papers from Semiconductor Engineering! 📄✨ 🛡Don’t miss out—explore and get guided by cutting-edge research. Follow Start With WCPGW #SemiconductorEngineering #TechPapers #ISCA #Research #Engineering #Innovation #TechTrends #startwithwcpgw #wcpgw

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TSMC Introduces “Foundry 2.0” to Include Packaging, Testing, Mask making and Others 💡 In the Q2 earnings call today (July 18th), #TSMC Chairman and CEO C.C. Wei introduced the concept of “Foundry 2.0,” redefining the #foundry industry to further include sectors like packaging, testing, mask making, and others, the latest report by Technews noted. C.C. Wei pointed out that under this new definition, TSMC’s foundry market share was 28% in 2023, and the foundry industry is expected to grow by 10% in 2024, while TSMC’s share will increase further. According to data from TrendForce, under the original definition of foundry, TSMC’s market share was 61.2%. On the other hand, the #semiconductor giant projects the entire #semiconductor market, excluding memory, to grow by 10% in 2024. Thanks again to TrendForce Corporation for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eiApxT4K #semiconductorindustry #semiconductormanufacturing #technology #it #tech #innovation #chip #chips #taiwan #ai #mobile #cpu #gpu #data

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As modern chip designs heavily rely on SRAM, its density plays a critical role in the scaling of advanced nodes. According to the ISSCC 2025 Advance Program, the SRAM density of Intel Corporation's 18A (1.8nm-class) process aligns more closely with TSMC’s N3 than its N2 (2nm-class) process. ◾ Key Metrics: ▪️ Intel 18A: SRAM bit cell size of 0.021 µm², achieving ~31.8 Mb/mm². ▪️ TSMC N2: SRAM bit cell size of 0.0175 µm², achieving ~38 Mb/mm². ▪️ Comparison: Intel’s 18A SRAM density marks a notable improvement over Intel 4 (0.024 µm²) but doesn’t match TSMC’s aggressive N2 scaling. ◾ Notable Features: ▪️ Both nodes incorporate gate-all-around (GAA) transistors, yet TSMC has aggressively reduced SRAM sizes compared to its FinFET-based predecessors. ▪️ Intel 18A introduces a backside power delivery network (BSPDN), enhancing power efficiency and logic density potential. ◾ Bigger Picture: While SRAM density is vital, logic density often has a greater impact on overall scaling and performance. However, comparative logic density data for Intel 18A and TSMC N2 remain undisclosed. As SRAM scaling becomes increasingly challenging due to design complexities and variability at smaller nodes, the focus shifts toward balancing SRAM density, power consumption, and logic performance. What’s your take on the SRAM vs. logic density debate in advanced process technologies? Thanks again to Tom's Hardware for the full article with more background and insights click the source link in the comments below. #Semiconductors #Intel18A #TSMCN2 #SRAMDensity #ProcessTechnology #AdvancedNodes #ChipDesign #TechInnovation

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Managing power is critical in chip design, but it's much more so when the power budgets extend into the kilowatt range. That was the focus of a recent panel at #61DAC, titled "Blackout - Managing kW Power Budgets," featuring industry leaders in IC design, EDA, IP, and system design. The discussion was both engaging and insightful, delving into the intricacies of power management in the high-performance and kW+ era. As HPC and AI workloads drive increased computing demands at an accelerating pace, design teams must adopt a multi-pronged approach to IC and systems power management for next-generation computing.   For those who missed the event, here are some key highlights from the panel: ● 𝐒𝐲𝐬𝐭𝐞𝐦 𝐚𝐧𝐝 𝐒𝐲𝐬𝐭𝐞𝐦-𝐨𝐟-𝐒𝐲𝐬𝐭𝐞𝐦 𝐂𝐨-𝐃𝐞𝐬𝐢𝐠𝐧: Understanding how incremental improvements contribute cumulatively across the entire design ecosystem. ● 𝐄𝐱𝐩𝐚𝐧𝐝𝐢𝐧𝐠 𝐒𝐢𝐥𝐢𝐜𝐨𝐧 𝐈𝐏’𝐬 𝐑𝐨𝐥𝐞: Examining how silicon IP is reshaping power consumption trajectories and its pivotal role in future advancements. ● 𝐍𝐞𝐱𝐭-𝐆𝐞𝐧, 𝐇𝐢𝐠𝐡-𝐃𝐞𝐧𝐬𝐢𝐭𝐲 𝐕𝐑𝐌𝐬: Investigating the expanded co-design possibilities of high-density VRMs for data centers and beyond. ● 𝟐.𝟓𝐃 𝐚𝐧𝐝 𝟑𝐃 𝐒𝐨𝐥𝐮𝐭𝐢𝐨𝐧𝐬: Addressing the nuanced thermal and power design challenges posed by these emerging technologies.   Thank you to our panelists and moderator:   Mo Faisal - Movellus Inc. Joseph C. Davis - Design with Calibre Trey Roessig - Empower Semiconductor Hans Yeager - Tenstorrent Moderated by: Ed Sperling - Semiconductor Engineering

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Centers focus on basic research to transform the energy efficiency of microelectronics and create microelectronics for extreme environments https://lnkd.in/g3r_6T_6 #MicroelectronicsScienceResearchCenters U.S. Department of Energy (DOE) 

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In this Electronic Design article, Qorvo’s Mike Zhu explores the challenges of high-voltage power conversion and the advantages of Qorvo’s cascode JFET SiC technology in ZVS applications. Read more: https://ow.ly/ggGs50TNxvh #JFET #SiC

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