Vidhi Agrawal

Vidhi Agrawal

Austin, Texas, United States
3K followers 500+ connections

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About

I am self-taught, result oriented and enthusiastic person with a flair for learning…

Activity

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Experience

  • Apple Graphic

    Apple

    Austin, Texas, United States

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    Santa Clara

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    Austin, Texas

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    Dallas, TX, United States

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    Bengaluru Area, India

Education

  • The University of Texas at Dallas Graphic

    The University of Texas at Dallas

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    Activities and Societies: Student Worker at International Risk and Safety Managment Department

    Currently, a graduate student specializing in emerging Digital and Analog Systems. This program provides extensive knowledge on development of VLSI chips which is integrated with practical experience.

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    Relevant Courses: Digital Signal Processing, Embedded Systems, Power Electronics, VLSI Technolgy and Design, Basic Electronics, Integrated Circuit and Design

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    Activities and Societies: President award in Scouts and Guides, Part of Winning Vollyball Team, Athlete

    http://agrasenvidyalaya.ac.in/

Licenses & Certifications

Volunteer Experience

  • Member

    TCS Maitree

    - 1 year

    Social Services

    TCS is an internal club which organize social events like blood donation camp, education, marathon, visit to old age home and dance for funds.
    I actively participated in these events and helped the club to promote and plan events.

  • SEWA Bharat Graphic

    Volutnteer

    SEWA Bharat

    - 6 months

    Education

    It is a national federation of SEWA organizations of women working in the informal economy.
    I used to visit the SEWA house where children from slum areas were brought by SEWA organization. We cooked food for them and teach them various habits which they need to implement in their daily lives. Also, we organised various workshops to share information about world growth.

  • President Award- Team Leader

    The Bharat Scouts and Guides

    - 8 years 1 month

    Social Services

    It is the national Scouting and Guiding association of India. It is voluntary, non-political, educational movement for young people helps in achieving their full physical, intellectual, emotional, social and spiritual potentials as individuals, as responsible citizens and as members of local, national and international communities. I served and achieved President's award for the same.

Courses

  • ASIC Design

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  • Advanced Digital Logic

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  • Advanced VLSI

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  • Analog Integrated Circuit Design

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  • Basic and Power Electronics

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  • C++

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  • Computer Architecture

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  • Deep Learning on FPGA

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  • Design and Analysis of Reconfigurable Systems- FPGA

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  • Digital Signal Processing

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  • Embedded Systems

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  • MEMS

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  • Microprocessor

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  • RF Systems

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  • Testing of Digital Circuits

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  • VLSI

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Projects

  • ASIC Design - Mini Stereo Digital Audio Processor Full Chip Design (MSDAP)

    • Developed RTL code for a high-speed and low power MSDAP chip, synthesized the design and, verified gate level netlist using ModelSim.
    • Floor planning, Placement & Routing, Clock Tree Synthesis, Optimization, Parasitic (RC) Extraction, Static Timing Analysis, IR Drop Analysis, Power Analysis.

  • Customizable Microprocessor design on FPGA with keyboard and VGA interface

    • Designed 16-bit customizable microprocessor using Verilog which can execute instructions (direct & memory mapped addressing modes), handle interrupts, communicate with IO devices and facilitates with expandable memory upto 16Mb (on board BRAM).
    • Instruction execution (Fetch -decode -Execute) takes 4 machine cycles and scalable to any custom instructions.

  • Ackermann Function implementation in FPGA

    • Hardware implementation of the most recursive Ackermann function on Zybo Zynq-7000 ARM/FPGA SoC Trainer Board.
    • Time and resource optimization.
    • Compared the performance with respect to execution time in software module by executing the same function using C.

  • Standard Cell Library Design

    • Implemented standard cells including INVERTER, NAND2, NOR2, XOR2, 2:1MUX, AOI22, OAI3222 and D Flip Flop.
    • Considered minimum area & minimum diffusion breaks.
    • Cadence Virtuoso - IBM 130nm, Synopsys- HSPICE, WaveView

  • High Speed and Low Power 14 Bit Multiplier

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    • 14 Bit Multiplier was designed with the emphasis on high speed and low power.
    • Used Booth's Algorithm, Compression Technique, and Carry Lookahead Adder.
    • Designed Schematic and Full Custom Layout using Cadence Virtuoso IBM 130nm..
    • Performed DRC and LVS check and extracted the netlist using QRC.
    • Verified functionality using Hspice simulation.
    • Characterized the necessary standard cells and compiled a library using SiliconSmart
    • Performed Static Timing and Power…

    • 14 Bit Multiplier was designed with the emphasis on high speed and low power.
    • Used Booth's Algorithm, Compression Technique, and Carry Lookahead Adder.
    • Designed Schematic and Full Custom Layout using Cadence Virtuoso IBM 130nm..
    • Performed DRC and LVS check and extracted the netlist using QRC.
    • Verified functionality using Hspice simulation.
    • Characterized the necessary standard cells and compiled a library using SiliconSmart
    • Performed Static Timing and Power Analysis using PrimeTime.
    • Achieved delay= 2.4ns and Power = 1.3mW.

  • Low Power SRAM Design

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    • Implemented schematic of SRAM that reads and writes 128 words with word size of 10 bits.
    • Features: Pre-decoded style row-column decoder, 8T memory cell array, Write Circuitry and, Sense Amplifier.
    • Proper sizing was done using the concept of Logical Effort.
    • Cadence Virtuoso Schematic editor- IBM 130nm.

  • Acceleration of General Purpose Approximate Programs Using Neural Networks and FPGAs

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    • Aimed to test and validate one of the several machine learning algorithms on computationally intensive hardware.
    • Generated training data for the neural network using C++.
    • Implemented machine learning algorithms on neural network using Verilog on ISE Design Suite and simulated using ISim simulator.
    • Performed the learning of neural network using software (FANN) for the generated data
    • Compared the performance of hardware and software implementation.
    • Achieved speedup…

    • Aimed to test and validate one of the several machine learning algorithms on computationally intensive hardware.
    • Generated training data for the neural network using C++.
    • Implemented machine learning algorithms on neural network using Verilog on ISE Design Suite and simulated using ISim simulator.
    • Performed the learning of neural network using software (FANN) for the generated data
    • Compared the performance of hardware and software implementation.
    • Achieved speedup of 100-500% without much loss of accuracy.

    Other creators

  • Trivium Cipher- Asynchronous stream cipher

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    • Trivium Cipher generates a key using 288 input bits consisting of three interconnected non-linear feedback shift registers.

    • Implemented full custom layout manually in three steps
    1) Multiplexers: To control flow of various inputs into the block.
    2) Shift registers: Three blocks of shift registers with different bit-lengths (93, 84, 111).
    3) Non-linear combinational logic: The block primarily consists of inverters, NOR-gates, XOR-gates.

    • Cadence Virtuoso IBM 130nm,…

    • Trivium Cipher generates a key using 288 input bits consisting of three interconnected non-linear feedback shift registers.

    • Implemented full custom layout manually in three steps
    1) Multiplexers: To control flow of various inputs into the block.
    2) Shift registers: Three blocks of shift registers with different bit-lengths (93, 84, 111).
    3) Non-linear combinational logic: The block primarily consists of inverters, NOR-gates, XOR-gates.

    • Cadence Virtuoso IBM 130nm, Synopsys- HSPICE, WaveView

    Other creators

  • Two Stage Fully Differential Operation Amplifier Design

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    • Designed two stage fully differential amplifier using Cadence Schematic- TSMC 350nm
    • Designed common source amplifier as the second stage to get higher swing.
    • Implemented Miller compensation to improve phase margin.
    • Used Cadence Spectre tool for simulation of gain, bandwidth, phase margin, slew rate, CMRR.

  • Image processing: Traffic sign board detection and extraction- MATLAB

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    • Detected the circular red colored board in different weather conditions using Canny Edge Detector and Hough Transform.
    • Detected numerical portion and segmented to extract individual number.
    • Trained the extracted number using Artificial Neural Network and recognized the data using OCR.

    Other creators

Languages

  • English

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  • Hindi

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  • Gujarati

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