Our paper on DRAM Microarchitecture and Characteristics at ISCA 2024

Is a logical qubit just like a physical qubit, but better? It depends on how closely you look. From afar, working with logical or physical qubits is very similar: - You describe a quantum circuit you want to run - You do a bit of compilation to adapt it to your target architecture. Ideally, there's even a compiler which does this automatically for you. - You run the resulting circuit and get your results If you have a circuit you're running on current hardware, there is a high chance it will run without modifications on a logical qubit architecture. But if you take a closer look, a lot of details change. 👉 First of all, the quality of the logical qubit depends on how many physical qubits are involved in building it. The more physical qubits you use, the better your logical qubit is supposed to be... but the fewer logical qubits you will have on a given chip. So, you need to find the right tuning. 👉 Then, the target gate set is different from the hardware you're used to. In particular, logical qubits can only execute discrete gates like the T gate, which induces a fixed pi/4 phase. Rotations are not native gates and must be approximated with a series of discrete gates. Because of the need to decompose rotation gates, the depth of your circuit can increase, sometimes significantly (1 to 2 orders of magnitude). And again, there is a right tuning to be found. If your approximation is too precise, the depth of your circuit will increase more than needed. This means longer run times and more errors. 👉 And even if you only use native gates, your algorithm's run time will depend on the physical chip's architecture. In particular, the T gate requires using "magic state factories". If your algorithm uses a lot of T gates and your chip doesn't have enough factories, execution will be slower than you would expect. 👉 But there are good sides too: logical qubits give you all-to-all connectivity, which is not always the case on physical qubits. And of course, you get lower error rates, which is why we want logical qubits in the first place. These are all things few people are considering today, since we're still a couple of years away from hardware featuring fully working logical qubits. But since logical qubits are bound to be required for useful quantum computers, I think the industry would benefit from looking at this more closely. One way you can do this is by using Alice & Bob's toolkit Felis, featuring what I believe is the first logical qubit emulator. Check out the first comment for a sample notebook showing how one can account for the discrete gate set and the tunable error rates.

Renumbering the Finite Volume polyMesh with Reverse Cuthill-McKee (RCM) results in a measurable reduction in matrix bandwidth, shrinking it from approximately 11.88 million to around 4,341 and clustering nonzero entries tightly around the diagonal (see also [1,2,3]). We verified this improvement on a 16-core CPU with 128 GB RAM running Ubuntu 22.04 LTS, drawing upon both iterative solver benchmarking and hardware performance counters (including L2/L3 cache misses). The following points summarize key insights, each supported by established literature on sparse matrix reordering and high-performance computing (HPC): -Performance Gains: Iterative solvers such as PCG and BiCG demonstrated 10–20% faster solve times, which aligns with prior bandwidth-minimization findings [1,3]. This enhancement stems from localized nonzero patterns near the diagonal that increase floating-point efficiency and reduce memory stalls [4]. -Cache Misses: By assigning numerically adjacent cells contiguously, the RCM-based BFS approach cut L2/L3 cache misses by up to 14%, confirmed via HPC profiling tools [3,5]. Lower cache miss rates have been repeatedly shown to accelerate sparse matrix-vector multiplications in CFD-like workloads [2,4]. -Storage Gains: The reordering slightly shrinks the overall memory footprint by ~6%—from about 4,200 MB to roughly 3,950 MB—as verified by system-level memory tracking. Similar compression of sparse matrix profiles has been documented to reduce overhead in large-scale computations [1,4]. These improvements mirror recognized best practices for sparse matrix bandwidth reduction, affirming that RCM-based reorderings can significantly boost solver performance and resource efficiency in OpenFOAM simulations [6]. --------------------------------------------------------------------------- References [1] Cuthill, E., & McKee, J. (1969). Reducing the bandwidth of sparse symmetric matrices. In Proceedings of the 1969 24th national conference (pp. 157-172). [2] Saad, Y. (2003). Iterative Methods for Sparse Linear Systems. SIAM. [3] George, A., & Liu, J. W. H. (1981). Computer Solution of Large Sparse Positive Definite Systems. Prentice-Hall. [4] Davis, T. A. (2006). Direct Methods for Sparse Linear Systems. SIAM. [5] Dongarra, J., Luszczek, P., & Petitet, A. (2003). The LINPACK Benchmark: Past, Present, and Future. Concurrency and Computation: Practice and Experience, 15(9), 803-820. [6] Moukalled, F., Mangani, L., & Darwish, M. (2016). The Finite Volume Method in Computational Fluid Dynamics. Springer.

𝐊𝐮𝐛𝐞𝐫𝐧𝐞𝐭𝐞𝐬 𝐑𝐞𝐬𝐨𝐮𝐫𝐜𝐞 𝐌𝐚𝐧𝐚𝐠𝐞𝐦𝐞𝐧𝐭🔥 In this article, you will learn about three different types of resource management. 1. Resource Quota 2. Resource Requests 3. Resource Limits 𝟏. 𝐑𝐞𝐬𝐨𝐮𝐫𝐜𝐞 𝐐𝐮𝐨𝐭𝐚 Resource quotas are native Kubernetes objects that impose limits on resource consumption. Administrators can set up resource quotas to control resource consumption on a 𝐩𝐞𝐫-𝐧𝐚𝐦𝐞𝐬𝐩𝐚𝐜𝐞 level, ensuring each namespace only uses a fair share of resources. 𝐄𝐱𝐚𝐦𝐩𝐥𝐞: ``` apiVersion: v1 kind: ResourceQuota metadata: name: cpu-memory-quota namespace: team-1 spec: hard: cpu: "12" memory: "8Gi" ``` This object will restrict the total number of CPUs requests in the "team-1" namespace to 12, and the memory is limited to 8Gi. Any combination of CPU/memory requests is allowed if the total number does not breach the limit defined in the Resource Quota. New pods will fail to deploy to the relevant namespace if the limit is reached. 𝟐. 𝐑𝐞𝐬𝐨𝐮𝐫𝐜𝐞 𝐑𝐞𝐪𝐮𝐞𝐬𝐭𝐬 Requests are used to specify the 𝐦𝐢𝐧𝐢𝐦𝐮𝐦 amount of resources( CPU & Memory ) that a Pod needs. Kubernetes uses these requests to decide which node to place the pod on, ensuring that the node has enough available resources to meet the pods requirements. Resource requests are defined in the spec.containers.resources.requests field of your pod manifests. 𝐄𝐱𝐚𝐦𝐩𝐥𝐞: ``` apiVersion: v1 kind: Pod metadata: name: requests-demo spec: containers: - name: nginx image: nginx:latest resources: requests: cpu: "100m" memory: "150Mi" ``` Requests don’t limit the actual resource usage of pods once they’re scheduled to nodes. Pods are free to use more CPU and memory than their requests allow when there is spare capacity on the node. 𝟑. 𝐑𝐞𝐬𝐨𝐮𝐫𝐜𝐞 𝐋𝐢𝐦𝐢𝐭𝐬 A limit is the maximum amount of resources that a container is allowed to use. When we do not configure a limit, Kubernetes automatically selects one. These limits help ensure that one Pod does not consume all the resources on a node, which could lead to performance degradation. 𝐄𝐱𝐚𝐦𝐩𝐥𝐞: ``` apiVersion: v1 kind: Pod metadata: name: limits-demo spec: containers: - name: nginx image: nginx:latest resources: limits: cpu: 100m memory: 150Mi ``` In the above example the pod has 100 millicores or 0.1 CPU core and 150Mi or 150 megabytes. It is important to set resource limits appropriately based on your application requirement. The more resources a Kubernetes cluster uses, the more 𝐞𝐱𝐩𝐞𝐧𝐬𝐢𝐯𝐞 it is to run. By correctly specifying our compute resource quota, requests and limits, we can reduce overspending, improve performance, and ensure efficient use of our Kubernetes resources. Stay tuned for further articles in which we will implement the above using hands-on. 👨💻 like👍Repost♻️ Follow Bala Vignesh Manoharan for more such posts 💯🚀 #kubernetes #resourceManagement

As soon as we learn about #quantumcomputing we face #quantum errors in computation. Immediately, we ask IF classical computation fails! Errors in communication or storage system is known and mostly resolved by redundancy or other techniques. However, error in computation is less known. Does the error occure? The answer is yes, but the error is very small and mitigated by engineering. However, as the server fleet increases and the chips become more complex, this may no longer be the case. Here is very interesting report about the "compute error" of classical systems. I am personally interested in "approximate computation" instead of exact computation.

Microarchitectural weird machines (µWM) can be used as a powerful obfuscation engine where computation operates based on events unobservable to conventional anti-obfuscation tools #computing #edu

Computer Architecture refers to the design and organization of a computer's internal components, including the relationships between them. It encompasses the way a computer processes, stores, and communicates information, and how it is controlled and coordinated. Computer Architecture involves the study of: 1. Instruction Set Architecture (ISA): The design of instructions that a computer can execute. 2. Microarchitecture: The organization of the CPU, including execution units, registers, and caches. 3. System Interconnects: The communication pathways between components, such as buses and networks. 4. Memory Hierarchy: The organization of memory levels, including cache, main memory, and storage. 5. Input/Output (I/O) Systems: The interfaces and protocols for interacting with external devices. 6. Parallel and Distributed Computing: The design of systems that use multiple processors or cores. Some key concepts in Computer Architecture include: 1. Von Neumann Model 2. Harvard Architecture 3. Pipelining 4. Superscalar Execution 5. Multithreading 6. Cache Memory 7. Virtual Memory 8. Parallel Processing Understanding Computer Architecture is crucial for: 1. Designing and optimizing computer systems 2. Improving performance, power efficiency, and reliability 3. Developing new technologies and innovations 4. Understanding the limitations and capabilities of computer systems.

Our recent papers on page migration in Hybrid DRAM-PCM memories. Hybrid memory systems with a combination of DRAM and Non-Volatile Memory (NVM) types can make use of scalability and performance of both NVM and DRAM. Random placement of pages in Phase Change Memory (PCM) with more write accesses incurs higher write latencies. So, migrating write intensive pages from PCM to DRAM helps to reduce execution time and memory response time for applications. However, to take advantage of this idea, the pages have to be migrated at the correct time during execution. In addition we need to take care of on-going memory accesses. Our recently published two papers address these issues: (1)  We give a QoS aware migration method that increases the chances of higher accesses to the migrated candidate pages; at the same time keeping regular service rate optimal. The work appears in the Journal of Systems Architecture. Title: "Migration-aware slot-based memory request scheduler to guarantee QoS in DRAM-PCM hybrid memories" Authors: Aswathy N S and Hemangee Kapoor (2) Identifying the migration candidate page normally depends on the access count. However, we observe that the temporal behaviour of the page is more important than its accumulated access count. In addition, if the page is not migrated within a give time frame, the benefits wil reduce. Towards this we propose a write intensity based migration method that also reverts the decision in case there are delays in migration. The work appears as an invited book chapter from the VLSI-SoC conference, published by Springer Nature Computer Science series. Title: "A Leap of Confidence: A Write Intensity aware Prudent Page Migration for Hybrid Memories" Authors: Aswathy N S, Aishwarya Gupta and Hemangee Kapoor

Is Mr Ben Eater ‘s 8 bit computer considered risc or cisc ? #chatgpt Ben Eater’s 8-bit breadboard computer is neither strictly RISC nor CISC, but it more closely resembles a RISC-like architecture due to its simplicity. Here’s why: Why It Resembles RISC 1. Simple and Minimal Instruction Set: • The instruction set of Ben Eater’s 8-bit computer is very small and basic. For example, instructions like ADD, OUT, or LDA perform straightforward operations without combining multiple tasks into one instruction. • This is a key characteristic of RISC: each instruction does one simple operation. 2. Explicit Load/Store: • Ben Eater’s computer separates memory access from computation. For instance: • LDA (Load Accumulator) loads data into the accumulator. • ADD performs arithmetic on data already in the accumulator. • This is similar to RISC’s load/store architecture, where memory operations and computation are kept separate. 3. Fixed Instruction Length: • Each instruction in Ben Eater’s computer is 8 bits long, which simplifies decoding. RISC architectures also typically have fixed-length instructions. 4. Focus on Simplicity: • The design prioritizes simplicity and ease of understanding over advanced functionality, much like RISC’s philosophy of keeping hardware and instruction execution straightforward. Why It Doesn’t Fully Fit RISC 1. No Advanced Pipelining: • Modern RISC architectures, like ARM or MIPS, are designed for pipelining, where multiple instructions are executed in overlapping stages. Ben Eater’s computer lacks pipelining, as it processes one instruction at a time. 2. Limited Register Usage: • RISC architectures typically have a large number of general-purpose registers. Ben Eater’s 8-bit computer primarily uses the accumulator for operations, which is more similar to early accumulator-based architectures (common before the RISC/CISC divide). Why It’s Not CISC 1. No Complex Instructions: • There are no instructions in Ben Eater’s computer that perform multi-step operations like combining memory access, arithmetic, and storage. For example, there’s no equivalent to a CISC instruction like ADD [NUM1], [NUM2]. • All operations must be broken into simple steps, as in RISC. 2. Simple Addressing Modes: • CISC architectures often include many addressing modes (e.g., immediate, indexed, indirect). Ben Eater’s computer uses very simple direct or immediate addressing, which aligns more with RISC. Conclusion While Ben Eater’s 8-bit computer doesn’t fully align with modern RISC or CISC architectures, its simplicity, minimal instruction set, and explicit load/store operations make it more similar to RISC in design and philosophy. It’s essentially a custom educational architecture built to demonstrate foundational computing principles.

Modular, scalable hardware architecture for a quantum computer

Cache Levels in Operating Systems: Caches play a critical role in improving system performance by reducing the time required to access frequently used data. In an operating system (OS), caches exist at multiple levels, primarily in hardware (CPU caches) and software (OS-managed caches). 👉 CPU Cache (Hardware Level) The CPU cache is a small, high-speed memory located close to the processor that stores frequently accessed data and instructions to reduce latency when fetching data from the main memory (RAM). 1️⃣ L1 Cache (Level 1) Closest to the CPU core and operates at the CPU clock speed. Split into two types: Instruction Cache (L1i): Stores instructions for execution. Data Cache (L1d): Stores data being processed. Smallest in size (16KB to 128KB per core) but fastest. 2️⃣ L2 Cache (Level 2) Larger than L1 but slower (lower clock speed). Unified (stores both data and instructions) or split like L1. Shared across cores in some architectures or dedicated per core. Size typically ranges from 256KB to several MB. 3️⃣ L3 Cache (Level 3) Shared among all cores of a CPU. Much larger than L1 and L2 but slower. Serves as a backup to reduce main memory access. Size ranges from several MB to tens of MB. 4️⃣ L4 Cache (Level 4) Rare and used in specialized processors. Typically off-chip and shared across the entire CPU. Acts as a bridge between the main memory and the CPU caches. ✅ Buffer Cache Managed by the OS to improve the performance of disk I/O operations. Stores frequently accessed disk blocks in memory (RAM) to reduce disk reads/writes. 1️⃣ Page Cache: Caches file system pages in RAM. Improves read/write performance for file systems. 2️⃣ Write-Back Cache: Writes data to the cache first and delays writing to the disk. Data can be lost if the system crashes before the data is written to disk. 3️⃣ Write-Through Cache: Ensures data is written to both the cache and disk simultaneously, reducing the risk of data loss. 💬 Virtual Memory Cache The OS manages virtual memory to provide an abstraction layer over physical memory. Uses Translation Lookaside Buffer (TLB) as a cache for virtual-to-physical memory address translations. TLB: Speeds up virtual memory operations by caching recent translations. Works closely with the CPU's MMU (Memory Management Unit). 💪 Cache Optimization in OS 1️⃣ Cache Replacement Policies: LRU (Least Recently Used): Replaces the least recently used data. FIFO (First In, First Out): Replaces the oldest data. Random Replacement: Randomly replaces cached data. 2️⃣ Cache Coherence: Ensures data consistency across multiple cores or processors. 3️⃣ Prefetching: Predictively loads data into the cache to reduce access latency. 4️⃣ Cache Partitioning: Allocates cache resources to specific cores or processes to avoid conflicts. Image source:Google #memory #kernel #operatingsystem #learning