Navneet Singh Rajput’s Post

🚀 Excited to Share My 40th YouTube #techshort! 🚀 In this tech short, explore how to write a constraint in SystemVerilog to generate an array where elements form a perfect mirror pattern. Learn this fascinating technique to enhance your constraint-writing skills! 🔔 Don't forget to like, share, and subscribe for more tech shorts! #vlsi #verification #semiconductors #verilog #systemverilog #asic #designverification #interviewpreparation #constraints #uvm #podcastwithnavneet #navneettechshorts #navneettechquiz #staytuned📚

🚀 Excited to Share My 47th YouTube #techshort! 🚀 In this tech short, explore how can we write a constraint to generate a number where the sum of its digits equals 15? Learn this fascinating technique to enhance your constraint-writing skills! 🔔 Don't forget to like, share, and subscribe for more tech shorts! #vlsi #verification #semiconductors #verilog #systemverilog #asic #designverification #interviewpreparation #constraints #uvm #podcastwithnavneet #navneettechshorts #navneettechquiz #staytuned📚

🚀 Excited to Share My 11th YouTube #techshort! 🚀 In this tech short, learn how to write a constraint to generate real numbers between 0 and 1 using SystemVerilog. Perfect for anyone looking to enhance their design verification skills and understanding of constraints in SystemVerilog. Don't forget to like, share, and subscribe for more tech shorts! #vlsi #verification #semiconductors #verilog #systemverilog #asic #designverification #interviewpreparation #constraints #uvm #podcastwithnavneet #navneettechshorts #staytuned 📚

what is the output of below code? module prg1(); reg [7:0]a; initial   begin   a = "A";   $display("Value of a %o",a); end endmodule #systemverilog #uvm #ovm #ral #axi #DV #DFT #verilog #code #coverage #semiconductor #vlsi #industry

🚀 Excited to Share My 10th YouTube #techshort! 🚀 Are you looking to enhance your SystemVerilog skills? Check out my latest YouTube short where I demonstrate how to write a constraint to generate odd numbers within the range of 20 to 50. This video is perfect for anyone aiming to sharpen their design verification skills, especially in writing constraints and working with arrays. Don't forget to like, share, and subscribe for more tech shorts! #vlsi #verification #semiconductors #verilog #systemverilog #asic #designverification #interviewpreparation #constraints #uvm #podcastwithnavneet #staytuned 📚

🚀 Excited to Share My 14th YouTube #techshort! 🚀 Are you curious about How a child class can override a parent class constraint in SystemVerilog? Check out my latest tech short where I dive into this concept and provide a practical example. 🔔 Don't forget to like, share, and subscribe for more tech shorts! #vlsi #verification #semiconductors #verilog #systemverilog #asic #designverification #interviewpreparation #constraints #uvm #oops #podcastwithnavneet #navneettechshorts #staytuned 📚

🚀 Randomizing Specific Bits in SystemVerilog 🎲 In SystemVerilog, it's often necessary to apply constraints to randomize specific bits of a value while leaving others unchanged. In this example, I demonstrate how to randomize the 12th bit of a 32-bit integer while ensuring the other bits remain fixed. This type of constraint-based randomization allows for precise control over the bits that need to vary, which is ideal for testing specific conditions in a verification environment. Key Insights: Targeted randomization of specific bits. Provides controlled testing with fixed values for other bits. Enhances efficiency in generating test vectors for digital designs. #SystemVerilog #Verification #Randomization #DesignVerification #VLSI #Testbenches #DigitalDesign

I came across this brilliant visual analogy that captures the difference between pass by value and pass by reference —a concept I recently explored in SystemVerilog. Just like in the example, passing by value creates a separate copy, leaving the original unchanged, while passing by reference allows you to interact with the original object directly!! #Systemverilog #HardwareDesign #Verification #PassByReference #PassByValue #CodingConcepts

🚀 Excited to Share My 3rd YouTube #techshorts! 🚀 In this short video, I demonstrate how to write a constraint to generate a Right-Sided Triangle Pattern in SystemVerilog? Don't forget to like, share, and subscribe for more tech shorts! #vlsi #verification #semiconductors #verilog #systemverilog #asic #designverification #interviewpreparation #constraints #podcastwithnavneet #staytuned 📚